Patents by Inventor Tarachand Pagarani

Tarachand Pagarani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9287868
    Abstract: A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: March 15, 2016
    Assignee: QuickLogic Corporation
    Inventors: Vishnu A. Patil, Wilma W. Shiao, Tarachand Pagarani, Pinaki Chakrabarti
  • Publication number: 20160065213
    Abstract: A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 3, 2016
    Inventors: Vishnu A. Patil, Wilma W. Shiao, Tarachand Pagarani, Pinaki Chakrabarti
  • Patent number: 9118325
    Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway and clock networks. Some of the switches include multiple stages. The feedback network switch receives signals from the logic island as well as from neighboring logic blocks and provides an output to one or more stages of the street network switch. The street network switch receives the signals from the feedback network switch and signals from neighboring highway network switches and provides an output to the logic island. A clock network switch may receive dedicated clock signals or high fan out signals as inputs and provides outputs to the street network switch. The highway network switch receives signals from the logic island and from neighboring highway network switches and provides an output to neighboring highway network switches.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: August 25, 2015
    Assignee: QuickLogic Corporation
    Inventors: Vishnu A. Patil, Karyampoodi Bhanu Prasanth, Wilma W. Shiao, Tarachand Pagarani, Pinaki Chakrabarti