Patents by Inventor Tarak A. Railkar
Tarak A. Railkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929300Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.Type: GrantFiled: February 23, 2023Date of Patent: March 12, 2024Assignee: Qorvo US, Inc.Inventors: Kevin J. Anderson, Andrew Arthur Ketterson, Tarak A. Railkar, Deep C. Dumka, Christo Bojkov
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Publication number: 20230395321Abstract: The present disclosure relates to a process to integrate sintered components in a laminate substrate. The disclosed process starts with providing a precursor substrate, which includes a substrate body having an opening through the substrate body, and a first foil layer. Herein, the first foil layer is formed underneath the substrate body, so as to fully cover a bottom of the opening. Next, a sinterable base material is applied into the opening and over the first foil layer, and then sintered at a first sintering temperature to create a sintered base component. A sinterable contact material is applied over the sintered base component, and then sintered at a second sintering temperature to create a sintered contact film. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on bottom, and by the sintered contact film on top.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
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Patent number: 11783998Abstract: The present disclosure relates to a process to integrate sintered components in a laminate substrate. The disclosed process starts with providing a precursor substrate, which includes a substrate body having an opening through the substrate body, and a first foil layer. Herein, the first foil layer is formed underneath the substrate body, so as to fully cover a bottom of the opening. Next, a sinterable base material is applied into the opening and over the first foil layer, and then sintered at a first sintering temperature to create a sintered base component. A sinterable contact material is applied over the sintered base component, and then sintered at a second sintering temperature to create a sintered contact film. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on bottom, and by the sintered contact film on top.Type: GrantFiled: August 16, 2019Date of Patent: October 10, 2023Assignee: Qorvo US, Inc.Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
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Publication number: 20230207415Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.Type: ApplicationFiled: February 23, 2023Publication date: June 29, 2023Inventors: Kevin J. Anderson, Andrew Arthur Ketterson, Tarak A. Railkar, Deep C. Dumka, Christo Bojkov
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Publication number: 20230178486Abstract: Backside metallization techniques for a semiconductor assembly are disclosed. In one aspect, a die, such as a radio frequency (RF) die, within a semiconductor package may include backside metallization for RF performance reasons. The metallization is generally planar and covers a surface of the RF die. Exemplary aspects of the present disclosure cause the metallization to include trenches or grooves to allow for better expansion and contraction during thermal cycling of the RF die. In particular, the trenches decrease a modulus of the metallization layer and act as a shock absorber and allow for compression and expansion of the metallization to match the compression and expansion of the non-metal substrate of the RF die. By allowing for better matching of the compression and expansion of the two heterogeneous materials, delamination may be delayed or averted.Type: ApplicationFiled: March 31, 2022Publication date: June 8, 2023Inventors: Tarak A. Railkar, Kevin J. Anderson, Tejpal Kaur Hooghan, Deep C. Dumka
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Patent number: 11626340Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.Type: GrantFiled: December 12, 2019Date of Patent: April 11, 2023Assignee: Qorvo US, Inc.Inventors: Kevin J. Anderson, Andrew Arthur Ketterson, Tarak A. Railkar, Deep C. Dumka, Christo Bojkov
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Patent number: 11551995Abstract: The present disclosure relates to a substrate that includes a substrate body and a thermoelectric cooler embedded in the substrate body. The thermoelectric cooler includes a top-side plate with an element-contact pad and a bottom-side plate. The element-contact pad is on a top surface of the top-side plate, which faces a same direction as a top surface of the substrate body and is exposed to the external space of the substrate body. The bottom-side plate is below the top-side plate and close to a bottom surface of the top-side plate. Herein, the element-contact pad is configured to accommodate attachment of a heat-generating electrical element. The top-side plate is configured to change temperature of the heat-generating electrical element, and the bottom-side plate is configured to transfer heat to or absorb heat from the bottom surface of the substrate body.Type: GrantFiled: October 15, 2018Date of Patent: January 10, 2023Assignee: Qorvo US, Inc.Inventors: Mark C. Woods, Kelly M. Lear, Deepukumar M. Nair, Tarak A. Railkar, Bradford Nelson
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Publication number: 20210183722Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.Type: ApplicationFiled: December 12, 2019Publication date: June 17, 2021Inventors: Kevin J. Anderson, Andrew Arthur Ketterson, Tarak A. Railkar, Deep C. Dumka
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Patent number: 10906274Abstract: The present disclosure relates to a laminate substrate with sintered components. The disclosed laminate substrate includes a substrate body having an opening through the substrate body, a first foil layer, a sintered base component, and a sintered contact film. The first foil layer is formed underneath the substrate body, such that a first portion of the first foil layer fully covers the bottom of the opening. The sintered base component is formed within the opening and over the first portion of the first foil layer. Herein, the sintered base component has a dielectric constant between 10 and 500, or has a relative permeability greater than 5. The sintered contact film is formed over the sintered base component. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on the bottom, and by the sintered contact film on the top.Type: GrantFiled: August 16, 2019Date of Patent: February 2, 2021Assignee: Qorvo US, Inc.Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
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Publication number: 20200147695Abstract: The present disclosure relates to a process to integrate sintered components in a laminate substrate. The disclosed process starts with providing a precursor substrate, which includes a substrate body having an opening through the substrate body, and a first foil layer. Herein, the first foil layer is formed underneath the substrate body, so as to fully cover a bottom of the opening. Next, a sinterable base material is applied into the opening and over the first foil layer, and then sintered at a first sintering temperature to create a sintered base component. A sinterable contact material is applied over the sintered base component, and then sintered at a second sintering temperature to create a sintered contact film. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on bottom, and by the sintered contact film on top.Type: ApplicationFiled: August 16, 2019Publication date: May 14, 2020Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
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Publication number: 20200147938Abstract: The present disclosure relates to a laminate substrate with sintered components. The disclosed laminate substrate includes a substrate body having an opening through the substrate body, a first foil layer, a sintered base component, and a sintered contact film. The first foil layer is formed underneath the substrate body, such that a first portion of the first foil layer fully covers the bottom of the opening. The sintered base component is formed within the opening and over the first portion of the first foil layer. Herein, the sintered base component has a dielectric constant between 10 and 500, or has a relative permeability greater than 5. The sintered contact film is formed over the sintered base component. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on the bottom, and by the sintered contact film on the top.Type: ApplicationFiled: August 16, 2019Publication date: May 14, 2020Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
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Patent number: 10587029Abstract: The present disclosure relates to a substrate that includes a substrate body and a resonator integrated within the substrate body. The resonator includes a resonator body, a top resonator plate, and a bottom resonator plate. The resonator body extends through the substrate body from a top surface to a bottom surface of the substrate body, and is formed of at least one of a dielectric material and a magnetic material. The top resonator plate is coupled to a top side of the resonator body and resides over the top surface of the substrate body, and the bottom resonator plate is coupled to a bottom side of the resonator body and resides over the bottom surface of the substrate body. The top resonator plate and the bottom resonator plate are electrically conductive.Type: GrantFiled: July 2, 2018Date of Patent: March 10, 2020Assignee: Qorvo US, Inc.Inventors: Jeffrey Dekosky, Deepukumar M. Nair, Scott M. Knapp, Tarak A. Railkar, Lawrence A. Carastro, Timothy G. Kraus
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Patent number: 10390434Abstract: The present disclosure relates to a microelectronic package, which includes a base substrate, a perimeter wall, an electronic component, and a mold compound. The perimeter wall extends from a periphery of the base substrate to form a cavity that is over the base substrate and within the perimeter wall. The electronic component is mounted on the base substrate and exposed to the cavity. The electronic component is thermally coupled to a thermal management component, which extends through the base substrate and conducts heat generated from the electronic component. The electronic component is also electrically coupled to a wall signal via, which extends through the perimeter wall and transmits signals. The mold compound resides over the base substrate and within the cavity, so as to encapsulate the electronic component.Type: GrantFiled: October 8, 2018Date of Patent: August 20, 2019Assignee: Qorvo US, Inc.Inventors: Kevin J. Anderson, Tarak A. Railkar, Walid M. Meliane
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Publication number: 20190131209Abstract: The present disclosure relates to a substrate that includes a substrate body and a thermoelectric cooler embedded in the substrate body. The thermoelectric cooler includes a top-side plate with an element-contact pad and a bottom-side plate. The element-contact pad is on a top surface of the top-side plate, which faces a same direction as a top surface of the substrate body and is exposed to the external space of the substrate body. The bottom-side plate is below the top-side plate and close to a bottom surface of the top-side plate. Herein, the element-contact pad is configured to accommodate attachment of a heat-generating electrical element. The top-side plate is configured to change temperature of the heat-generating electrical element, and the bottom-side plate is configured to transfer heat to or absorb heat from the bottom surface of the substrate body.Type: ApplicationFiled: October 15, 2018Publication date: May 2, 2019Inventors: Mark C. Woods, Kelly M. Lear, Deepukumar M. Nair, Tarak A. Railkar, Bradford Nelson
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Publication number: 20190116670Abstract: The present disclosure relates to a microelectronic package, which includes a base substrate, a perimeter wall, an electronic component, and a mold compound. The perimeter wall extends from a periphery of the base substrate to form a cavity that is over the base substrate and within the perimeter wall. The electronic component is mounted on the base substrate and exposed to the cavity. The electronic component is thermally coupled to a thermal management component, which extends through the base substrate and conducts heat generated from the electronic component. The electronic component is also electrically coupled to a wall signal via, which extends through the perimeter wall and transmits signals. The mold compound resides over the base substrate and within the cavity, so as to encapsulate the electronic component.Type: ApplicationFiled: October 8, 2018Publication date: April 18, 2019Inventors: Kevin J. Anderson, Tarak A. Railkar, Walid M. Meliane
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Publication number: 20190074571Abstract: The present disclosure relates to a substrate that includes a substrate body and a resonator integrated within the substrate body. The resonator includes a resonator body, a top resonator plate, and a bottom resonator plate. The resonator body extends through the substrate body from a top surface to a bottom surface of the substrate body, and is formed of at least one of a dielectric material and a magnetic material. The top resonator plate is coupled to a top side of the resonator body and resides over the top surface of the substrate body, and the bottom resonator plate is coupled to a bottom side of the resonator body and resides over the bottom surface of the substrate body. The top resonator plate and the bottom resonator plate are electrically conductive.Type: ApplicationFiled: July 2, 2018Publication date: March 7, 2019Inventors: Jeffrey Dekosky, Deepukumar M. Nair, Scott M. Knapp, Tarak A. Railkar, Lawrence A. Carastro, Timothy G. Kraus
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Patent number: 10217686Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.Type: GrantFiled: March 26, 2018Date of Patent: February 26, 2019Assignee: Qorvo US, Inc.Inventors: Walid M. Meliane, Kevin J. Anderson, Tarak A. Railkar
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Patent number: 10177064Abstract: The present disclosure relates to an air-cavity package, which includes a substrate, a base, and a semiconductor die. The substrate includes a substrate body, thermal vias extending through the substrate body, and a metal trace on a bottom side of the substrate body and separate from the thermal vias. The base includes a base body, a perimeter wall extending about a perimeter of the base body, and a signal via structure. Herein, the bottom side of the substrate body resides on the perimeter wall to form a cavity, and the signal via structure extends through the perimeter wall and is electrically coupled to the metal trace. The semiconductor die is mounted on the bottom side of the substrate body, exposed to the cavity, and electrically coupled to the metal trace. The thermal vias conduct heat generated from the semiconductor die toward a top side of the substrate body.Type: GrantFiled: November 30, 2016Date of Patent: January 8, 2019Assignee: Qorvo US, Inc.Inventors: Kevin J. Anderson, Anthony Chiu, Tarak A. Railkar
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Patent number: 10141245Abstract: The present disclosure relates to a high-power acoustic device with improved performance. The disclosed acoustic device includes a substrate, a die-attach material, and an acoustic die. The substrate includes a substrate body and a die pad on a top surface of the substrate body. The die-attach material is a sintered material and applied over the die pad. The acoustic die is coupled to the die pad via the die-attach material. Herein, the acoustic die includes a die body and a metallization structure, which is sandwiched between the die body and the die-attach material.Type: GrantFiled: August 24, 2017Date of Patent: November 27, 2018Assignee: Qorvo US, Inc.Inventors: Tarak A. Railkar, Ian Y. Yee, Jeffrey D. Galipeau, Jason Wu, Rodolfo E. Chang
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Patent number: 10096536Abstract: Various technologies presented herein relate to forming one or more heat dissipating structures (e.g., heat spreaders and/or heat sinks) on a substrate, wherein the substrate forms part of an electronic component. The heat dissipating structures are formed from graphene, with advantage being taken of the high thermal conductivity of graphene. The graphene (e.g., in flake form) is attached to a diazonium molecule, and further, the diazonium molecule is utilized to attach the graphene to material forming the substrate. A surface of the substrate is treated to comprise oxide-containing regions and also oxide-free regions having underlying silicon exposed. The diazonium molecule attaches to the oxide-free regions, wherein the diazonium molecule bonds (e.g., covalently) to the exposed silicon. Attachment of the diazonium plus graphene molecule is optionally repeated to enable formation of a heat dissipating structure of a required height.Type: GrantFiled: June 8, 2017Date of Patent: October 9, 2018Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Cody M. Washburn, Timothy N. Lambert, David R. Wheeler, Christopher T. Rodenbeck, Tarak A. Railkar