Abstract: An ear examination tool comprises a handle and a speculum mount coupled to the handle. The speculum mount is configured for retaining a disposable speculum. An spacing element is coupled to the handle and extends from the handle. A smartphone mount is coupled to the spacing element, and the spacing element is configured to maintain an optical separation distance between the speculum mount and the smartphone mount. The tool enables a clear view of the ear canal while allowing access by, and manipulation of, a microsuction tool being inserted into the ear canal. The extensive optical and data processing functionality of a “smartphone” can be integrated at low cost into an ear examination tool to provide a substantially improved piece of equipment for assisting in ear examination and microsuction of the ear.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and splitting, using the at least one processor, the electronic design schematic into a plurality of subcircuits. Embodiments may further include independently simulating each of the plurality of subcircuits to generate simulation results and analyzing the simulation results to determine over-stress associated with the plurality of subcircuits.

Abstract: An ear examination tool comprises a handle and a speculum mount coupled to the handle. The speculum mount is configured for retaining a disposable speculum. An spacing element is coupled to the handle and extends from the handle. A smartphone mount is coupled to the spacing element, and the spacing element is configured to maintain an optical separation distance between the speculum mount and the smartphone mount. The tool enables a clear view of the ear canal while allowing access by, and manipulation of, a microsuction tool being inserted into the ear canal. The extensive optical and data processing functionality of a “smartphone” can be integrated at low cost into an ear examination tool to provide a substantially improved piece of equipment for assisting in ear examination and microsuction of the ear.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include providing, using at least one processor, an electronic circuit design including an integrated circuit (“IC”) or package schematic and generating a power distribution network (“PDN”) based upon at least in part, the electronic circuit design including the IC or package. The method may further include obtaining a PDN model having one or more port mappings between one or more layout terminals and one or more schematic pin-names and stitching the PDN model and the IC or package schematic into a combined PDN and IC or package schematic model. The method may also include simulating the combined PDN and IC or package schematic model using the at least one processor.

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.

Abstract: Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

Abstract: Embodiments included herein are directed towards a system and method for implementing an IC package design with an IC package design estimator. Embodiments may include estimating a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs. Embodiments may further include determining whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die designs. Embodiments may also include identifying a number of layers required to perform routing between each of the plurality of IC die designs. Embodiments may further include determining a power layer or ground layer based upon, at least in part, one or more factors and generating an output for the IC package design based upon, at least in part, the estimated number of layers and the power layer or ground layer.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Abstract: Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.

Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Abstract: The present disclosure relates to a system and method for simulating channels in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design including at least one channel. Embodiments may further include transmitting two or more inputs from two or more transmitter drivers on two or more wires to the at least one channel. In some embodiments, the inputs may be distributed across the wires based upon a chordal code. Embodiments may also include generating simulated waveforms based upon the inputs. Embodiments may further include transmitting the simulated waveforms from the channel on the wires to a comparator block. Embodiments may also include comparing the simulated waveforms on the wires at the comparator block to produce two or more simulated outputs. Embodiments may include transmitting the simulated outputs from the comparator block on the wires to two or more post-comparator receivers.

Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

Abstract: Disclosed are techniques for generating a parasitic-aware simulation schematic across multiple design fabrics. These techniques identify a first extracted model from existing extracted models for a first circuit component design in a first layout in a first design fabric of an electronic design that spans across multiple design fabrics. These techniques further generate a simulation schematic by inserting the first extracted model into the simulation schematic. In addition, a simulation may be performed with the simulation schematic to generate simulation results. Schematic models, if existing, may also be used to revise the simulation schematic. For circuit component designs corresponding to no extract models or schematic models, one or more extracted models placeable in the simulation schematic may also be constructed to update the simulation schematic.

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.

Abstract: Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.

Abstract: Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package layout design based using at least the estimated number of layers and the power layer and/or the ground layer. These mechanisms use input including connectivity information, thermal effects, and/or IC placement information to determine estimates for the total number of layers, layer stack-up, power and ground plane assignment, and via libraries to guide IC package layout design.

Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.