Abstract: Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.

Abstract: Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.

Abstract: A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.

Abstract: Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.

Abstract: Techniques for capacitance extraction from an integrated circuit design are provided. In one aspect, a method for determining coupling capacitance between conductors within an integrated circuit design is provided comprising the following steps. A three-dimensional representation of the integrated circuit design is generated based on three-dimensional technology and three-dimensional geometric input about the integrated circuit. Conductors of interest are selected from the design. Three-dimensional coupling capacitance between the selected conductors is determined. Further, a first and a second conductor can be selected from the conductors of interest. A Gaussian surface can be created around the first conductor. A random walk path can be created starting at a randomly selected point on the Gaussian surface and terminating on the second conductor.

Abstract: Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.

Abstract: A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.