Patents by Inventor Tarek Chaker Jomaa

Tarek Chaker Jomaa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Variable rotational assignment of interconnect levels in integrated circuit fabrication
    Patent number: 7042079
    Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: May 9, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Thaddeus John Gabara, Tarek Chaker Jomaa
  • Variable rotational assignment of interconnect levels in integrated circuit fabrication
    Patent number: 6849937
    Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: February 1, 2005
    Assignee: Lucent Technologies Inc.
    Inventors: Thaddeus John Gabara, Tarek Chaker Jomaa
  • Variable rotational assignment of interconnect levels in integrated circuit fabrication
    Publication number: 20030141584
    Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.
    Type: Application
    Filed: February 28, 2003
    Publication date: July 31, 2003
    Applicant: Lucent Technologies Inc.
    Inventors: Thaddeus John Gabara, Tarek Chaker Jomaa
  • Variable rotational assignment of interconnect levels in integrated circuit fabrication
    Patent number: 6586281
    Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: July 1, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Thaddeus John Gabara, Tarek Chaker Jomaa