Patents by Inventor Tarek M. Taha

Tarek M. Taha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210019610
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrixvalues included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in theweighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 21, 2021
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Publication number: 20210019597
    Abstract: A spiking neural network (SNN) system is disclosed having spiking neurons associated with clause values associated with a satisfiability (SAT) problem. Each spiking neuron generates a voltage spike when on input voltage applied to each spiking neuron is increased above a spiking voltage threshold. The input voltage that is increased above the spiking voltage threshold is indicative that the corresponding clause value is satisfied. A controller applies the clause grid that includes clause values to a literal grid that includes literal values. The controller generates the input voltage that is applied to each spiking neuron based on each corresponding clause value associated with each spiking neuron that is applied to the literal values. The controller determines that each clause value is satisfied when the corresponding spiking neuron generates the voltage spike and that each clause value is unsatisfied when the corresponding spiking neuron fails to generate the voltage spike.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 21, 2021
    Inventors: Chris Yakopcic, Tarek M. Taha
  • Patent number: 10885429
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: January 5, 2021
    Assignee: University of Dayton
    Inventors: Tarek M. Taha, Raqibul Hasan, Chris Yakopcic
  • Publication number: 20200364550
    Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
    Type: Application
    Filed: June 1, 2020
    Publication date: November 19, 2020
    Inventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
  • Patent number: 10789528
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 29, 2020
    Assignee: University of Dayton
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Patent number: 10671914
    Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: June 2, 2020
    Assignee: University of Dayton
    Inventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
  • Patent number: 10622064
    Abstract: A crossbar circuit determines a match of N bits of data to at least one of M target words simultaneously. The circuit comprises N inputs (one per data bit) and M outputs (one per target word). For each of the M target words, the circuit comprises N?1 biased bits, where each biased bit includes a first data memristor coupled to a corresponding one of the N inputs; a second data memristor coupled to the corresponding one of the N inputs, where the corresponding one of the N inputs is inverted before reaching the second data memristor; and two biasing memristors. Further, the circuit comprises a general bit comprising a first data memristor coupled to the input that does not correspond to any of the biased bits; and a second data memristor coupled to the input that does not correspond to any of the biased bits and is inverted.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 14, 2020
    Assignee: University of Dayton
    Inventors: Tarek M. Taha, Chris Yakopcic
  • Publication number: 20200074291
    Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
  • Patent number: 10474948
    Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: November 12, 2019
    Assignee: University of Dayton
    Inventors: Chris Yakopcic, Raqibul Hasan, Tarek M. Taha
  • Publication number: 20190332930
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Publication number: 20190228822
    Abstract: A crossbar circuit determines a match of N bits of data to at least one of M target words simultaneously. The circuit comprises N inputs (one per data bit) and M outputs (one per target word). For each of the M target words, the circuit comprises N?1 biased bits, where each biased bit includes a first data memristor coupled to a corresponding one of the N inputs; a second data memristor coupled to the corresponding one of the N inputs, where the corresponding one of the N inputs is inverted before reaching the second data memristor; and two biasing memristors. Further, the circuit comprises a general bit comprising a first data memristor coupled to the input that does not correspond to any of the biased bits; and a second data memristor coupled to the input that does not correspond to any of the biased bits and is inverted.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 25, 2019
    Inventors: Tarek M. Taha, Chris Yakopcic
  • Patent number: 10346738
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: July 9, 2019
    Assignee: University of Dayton
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Publication number: 20190138894
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 9, 2019
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Patent number: 10176425
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: January 8, 2019
    Assignee: University of Dayton
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Publication number: 20180018559
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 18, 2018
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Publication number: 20170011290
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 12, 2017
    Inventors: Tarek M. Taha, Raqibul Hasan, Chris Yakopcic
  • Publication number: 20160284400
    Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
    Type: Application
    Filed: March 28, 2016
    Publication date: September 29, 2016
    Inventors: Chris Yakopcic, Raqibul Hasan, Tarek M. Taha
  • Publication number: 20150213884
    Abstract: A resistive memory array partitioned into a plurality of memory units is disclosed. Each memory unit includes a plurality of resistive memory elements, a plurality of row lines, a plurality of column lines, a plurality of row select switching devices, and a plurality of column select switching devices. Each resistive memory element is in communication with one of the row lines and one of the column lines. Each row line is in communication with a corresponding one of the row select switching devices. Each column line is in communication with a corresponding one of the column select switching devices.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 30, 2015
    Applicant: UNIVERSITY OF DAYTON
    Inventors: Tarek M. Taha, Chris Yakopcic