Abstract: A method and device for monitoring an avionics software application via its execution duration, related computer program and avionics system are disclosed. In one aspect, the method, executed on a platform hosting an operating system, is implemented by an electronic monitoring device. The avionics software application includes one or several software processing operations to be executed, the platform is configured to be on board an aircraft. The method includes: monitoring the execution duration of the avionics software application, through the verification, upon expiration of at least one predefined execution times, of the completion of the execution of at least one software processing operation of the avionics software application; and updating a status of the avionics software application based on the monitoring of the execution duration of the avionics software application.

Abstract: The invention relates to a message exchange controller structure (1) comprising means (3) forming a message exchange controller, associated with a member (4) forming a storage/exchange buffer, a member (5) forming interfaces for multiple connections to several message production/consumption units, and a member (6) forming interfaces for connecting to several external buses; which is characterized in that the means exchange controller-forming means (3) are able to recover redundant messages from external buses, store those messages in the storage/exchange buffer-forming member (4), recover those messages from the storage/exchange buffer-forming member (4), and process those messages so as to generate a resultant message (MF), to send it to at least one consumption unit.

Abstract: A generic and multi-role controller structure for data and communication exchanges is disclosed. In one aspect, the structure assumes the form of a single component and includes a capability forming a generic data and communication exchange controller, associated with at least: a capability forming a data storage/exchange buffer, a capability forming multiple connection interfaces to several data production/consumption units, one connection interface being associated with one data production/consumption unit, a capability forming multiple connection interfaces with several external data communication buses, and one connection interface being associated with one external data communication bus.

Abstract: A network having a plurality of electronic equipments and a plurality of network nodes is disclosed. The nodes are connected and form a reference ring, according to which ring the nodes are ordered by successive ranks. Each node is connected by a direct receiving connection to an upstream node and via a direct transmission connection to a downstream node. The network is adapted to tolerate a number of network node breakdowns, n being greater than 1. Each node is connected by a direct receiving connection to all of the other nodes placed, in the reference ring, up to: 2 ranks downstream and 1 rank upstream or 1 rank downstream and 2 ranks upstream if n is 2; n?1 ranks downstream and n?1 ranks upstream, if n is odd; or n?1 ranks downstream and n?2 ranks upstream, or n?2 ranks downstream and n?1 ranks upstream, if n is even and greater than 2.

Abstract: A method and a device for the detection of erroneous or inopportune transactions of any entity of a microprocessor or microcontroller includes programming counters internal or external to the microcontroller, which is configured to count the number of transactions in the target area of the target interface of the microcontroller; count the total number of transactions on the target interface, and verify that the number of transactions outside of the target area of the target interface of the microcontroller is zero. Equality between the number of transactions in the target area of the target interface and the total number of transactions on the target interface of the microcontroller is verified.

Abstract: A network having a plurality of electronic equipments and a plurality of network nodes is disclosed. The nodes are connected and form a reference ring, according to which ring the nodes are ordered by successive ranks. Each node is connected by a direct receiving connection to an upstream node and via a direct transmission connection to a downstream node. The network is adapted to tolerate a number of network node breakdowns, n being greater than 1. Each node is connected by a direct receiving connection to all of the other nodes placed, in the reference ring, up to: 2 ranks downstream and 1 rank upstream or 1 rank downstream and 2 ranks upstream if n is 2; n-1 ranks downstream and n-1 ranks upstream, if n is odd; or n-1 ranks downstream and n-2 ranks upstream, or n-2 ranks downstream and n-1 ranks upstream, if n is even and greater than 2.

Abstract: The present invention relates to computers, the undetected errors of which have a very low rate of occurrence (approximately 10?9 per time unit). This relates in particular to the embedded computers on aircraft that run critical applications such as the automatic pilot, flight management, fuel management or terrain collision prevention. Two or more computation lanes or sections are provided and the exchanges are authorized either on the production or on the consumption of the data by each of the lanes. It is also possible to provide a predefined authorization cycle. The authorization to transfer the datum is given according to a binary comparison logic in the case of two lanes. In the case of more than two lanes, the authorization can be given either by a binary comparison logic or by a majority logic depending on whether the integrity or the availability of the computation system is prioritized.