Abstract: This disclosure may prevent unauthorized modification of country code information stored in a wireless device including a high-level operating system (HLOS) and a radio subsystem including at least a first radio and a second radio. The first radio may receive first country code information from the HLOS, and may receive a message from the second radio. The message may include second country code information and a digital signature. The first radio may verify the message based on the digital signature, and may determine a validity of the first country code information based on a comparison with the second country code information. Transmission parameters of the wireless device may be configured using either the first or second country code information in response to the verifying.

Abstract: A hardware pixel processing pipeline and a video processing instruction set accelerate image processing and/or video decompression. The pixel processing pipeline uses hardware components to more efficiently perform color space conversion and horizontal upscaling. Additionally, the pixel processing pipeline also reduces the size of its output data to conserve bandwidth. A specialized video processing instruction set allows further acceleration of video processing or video decoding by allowing receipt of a single instruction to cause multiple addition operation or interpolation of multiple pairs of pixels in parallel.

Abstract: A hard real time (HRT) thread scheduler and a non-real time (NRT) thread scheduler for allocating processor resources among HRT threads and NRT threads are disclosed. The HRT thread scheduler communicates with a HRT thread table including a plurality of entries specifying a temporal order for allocating execution cycles to one or more HRT threads. If a HRT thread identified by the HRT thread table is unable to be scheduled during the current execution cycle, the NRT thread scheduler accesses an NRT thread table which includes a plurality of entries specifying a temporal order for allocating execution cycles to one or more NRT threads. In an execution cycle where a HRT thread is not scheduled, the NRT thread scheduler identifies an NRT thread from the NRT thread table and an instruction from the identified NRT thread is executed during the execution cycle.

Abstract: A hardware pixel processing pipeline and a video processing instruction set accelerate image processing and/or video decompression. The pixel processing pipeline uses hardware components to more efficiently perform color space conversion and horizontal upscaling. Additionally, the pixel processing pipeline also reduces the size of its output data to conserve bandwidth. A specialized video processing instruction set allows further acceleration of video processing or video decoding by allowing receipt of a single instruction to cause multiple addition operation or interpolation of multiple pairs of pixels in parallel.

Abstract: A hard real time (HRT) thread scheduler and a non-real time (NRT) thread scheduler for allocating allocate processor resources among HRT threads and NRT threads are disclosed. The HRT thread scheduler communicates with a HRT thread table including a plurality of entries specifying a temporal order for allocating execution cycles are allocated to one or more HRT threads. If a HRT thread identified by the HRT thread table is unable to be scheduled during the current execution cycle, the NRT thread scheduler accesses an NRT thread table which includes a plurality of entries specifying a temporal order for allocating execution cycles to one or more NRT threads. In an execution cycle where a HRT thread is not scheduled, the NRT thread scheduler identifies an NRT thread from the NRT thread table and an instruction from the identified NRT thread is executed during the execution cycle.

Abstract: A system for and method of controlling an electronic display, such as an electrophoretic display, using an integrated electronic paper display controller are disclosed. The system and method provide for transparent translation of standard image data into signals sufficient to drive such displays and implement the corresponding image.

Abstract: A system for synchronization of data processing in a data processing system including multiple command queues is disclosed. The disclosed data processing system includes one or more processing engines associated with one or more command queues. The use of multiple command queues supports multiple priority levels, such that commands in higher priority queues may preempt commands in lower priority queues. Data processing is synchronized by queue commands that allow a processing engine to queue commands on the command queue of any processing engine in the data processing system, including its own. Multiple data dependencies are resolved by conditional queue commands and event counters that queue a command only when all of the conditions precedent to execution of a particular data processing command are satisfied. The hardware queuing of the disclosed invention advantageously synchronizes data processing with minimal software supervision and with minimal latency.

Abstract: A memory device for a digital video system, capable of receiving video data in a packed format and transmitting that video data in a planar format. In other operating modes, the memory device receives video data in various packed formats and transmits that video data in a packed format. The memory device is suitable for a flexible digital video system in which video data may either be displayed in real time as it is generated (using packed format data) or compressed for storage and future display (using planar format data).