Abstract: One or more examples relate, generally to phase and frequency error processing. An apparatus includes a phase path and a frequency path. The phase path processes phase error of communications between network nodes. The phase path includes a closed-loop feedback loop controller. The frequency path processes frequency error of the communications between the network nodes. The frequency path is separate from the phase path. A method of processing phase error and frequency error includes selecting first packets for phase processing, processing the first packets for phase error, selecting second packets for frequency processing, and processing the second packets for frequency error independently of the processing of the first packets.

Abstract: A clock recovery device recovers frequency and timing information from an incoming packet stream over asynchronous packet networks. A phase locked loop (PLL) block has predefined states and includes a type II PLL. One of the states involves type II PLL operation. A state machine controller for controls the transition between the predefined states in response to changes in the incoming packet stream. A controlled oscillator is responsive to the PLL block to generate an output signal.

Abstract: A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.

Abstract: A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.

Abstract: In a closed loop acoustic system with forward and return paths, gain is controlled with different instantiations of a common gain control engine on each path. The gain control engine computes a first gain based on near-end signal levels, computes a second gain based on the output of the gain control engine, computes a third gain based on a howling condition, and computes a final gain as the product of the first, second and third gains.