Abstract: Systems and methods include technology that divides first data associated with a first matrix into first multiplication tiles based on a block size that is identified based on an available space of a memory of an accelerator, and second data associated with a second matrix into second multiplication tiles based on the block size. The technology divides the first multiplication tiles into a plurality of first groups that correspond to a plurality of matrix multiplication operations and the second multiplication tiles into a plurality of second groups that correspond to the plurality of matrix multiplication operations. The technology loads a selected first multiplication tile of the first multiplication tiles and a selected second multiplication tile of the second multiplication tiles into the memory to execute one or more of the plurality of matrix multiplication operations with selected groups of the first plurality of groups and the second plurality of groups.

Abstract: Methods, apparatus, systems, and articles of manufacture to process web-scale graphs are disclosed. An example apparatus comprises: at least one memory; instructions; and processor circuitry to execute the instructions to: retrieve a compute based tile (CBT) from a first external memory, the CBT to include source and destination nodes of a graph; assign a stripe of the CBT to a single instruction multiple data compute unit, the stripe including a first tile and a second tile, the first tile to include first destination nodes and first source nodes, the second tile to include the first destination nodes and second source nodes; retrieve source node embeddings of the stripe based on a node identifier to source node embedding lookup; and provide the source node embeddings to the single instruction multiple data compute unit.

Abstract: Graph reordering and tiling techniques are described herein. In one example, large graphs (e.g., for inferencing with graph neural networks) can be reordered, tiled, or both, to achieve maximal data reuse and uniform compute load distribution. In one example, a reordering method involves performing breadth first search (BFS) renumbering on a graph data set with the highest degree destination node as the root node to generate a reordered graph data set. BFS is then performed again with candidate nodes from the last level of the reordered graph. The second reordered graph data set with the lowest bandwidth or best profile can be selected for further processing. In one example, a method of tiling involves dividing a graph data set into tiles to balance expected compute time.

Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.

Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.

Abstract: A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).

Abstract: A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-O to 104-N) that provide a received test data to logic adjust circuits (106-O to 106-N) that “logically align” multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit (108) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit (110).

Abstract: A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).