Patents by Inventor Tark-Hyun KO

Tark-Hyun KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607905
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Publication number: 20190295909
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: Baek KI, Tark-Hyun KO, Kun-Dae YEOM, Yong-Kwan LEE, Keun-Ho JANG, Sang Jin HYUN
  • Patent number: 10361135
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Publication number: 20180076105
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Application
    Filed: July 4, 2017
    Publication date: March 15, 2018
    Inventors: Baek KI, Tark-Hyun KO, Kun-Dae YEOM, Yong-Kwan LEE, Keun-Ho JANG