Patents by Inventor Tark Wooi Fong

Tark Wooi Fong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7034555
    Abstract: A shielded test contactor to electrically couple a device to be tested to test circuitry, comprises conductive material covered by or embedded in non-conductive material and defining a well to receive the device. Contacts extend from the embedded conductive material to connect the embedded conductive material to ground. Preferably, the contacts are extensions of the conductive material, through the non-conductive material. A second non-conductive material is preferably provided to support the embedded conductive material and define a floor of the well. Electrical connectors are preferably also supported by the second non-conductive material adjacent to the well, to electrically couple the device to test circuitry. For example, the connectors may be pins supported by the second non-conductive material and extending into the well. Preferably, the height of the conductive material defining the well is at least twice the height of the device to be tested.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Fern Nee Tan, Suk Yeak Lai, Tark Wooi Fong
  • Patent number: 6911833
    Abstract: A shielded test contactor to electrically couple a device to be tested to test circuitry, comprises conductive material covered by or embedded in non-conductive material and defining a well to receive the device. Contacts extend from the embedded conductive material to connect the embedded conductive material to ground. Preferably, the contacts are extensions of the conductive material, through the non-conductive material. A second non-conductive material is preferably provided to support the embedded conductive material and define a floor of the well. Electrical connectors are preferably also supported by the second non-conductive material adjacent to the well, to electrically couple the device to test circuitry. For example, the connectors may be pins supported by the second non-conductive material and extending into the well. Preferably, the height of the conductive material defining the well is at least twice the height of the device to be tested.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: June 28, 2005
    Assignee: Intel Corporation
    Inventors: Fern Nee Tan, Suk Yeak Lai, Tark Wooi Fong
  • Patent number: 6885207
    Abstract: An apparatus including a circuit substrate having a plurality of contactor pins extending between two opposing surfaces; and at least one capacitor mounted on one of the two opposing surfaces of the circuit substrate.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong
  • Publication number: 20030206033
    Abstract: An apparatus including a circuit substrate having a plurality of contactor pins extending between two opposing surfaces; and at least one capacitor mounted on one of the two opposing surfaces of the circuit substrate.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 6, 2003
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong
  • Patent number: 6597190
    Abstract: An apparatus for testing electronic devices such as integrated circuits. In one embodiment, an apparatus for testing electronic devices is disclosed that includes a housing such as a test contactor housing which has a plurality of test contactor pins that extend therethrough. The plurality of test contactor pins include a first set of power pins, a second set of ground pins, and a third set of signal pins. A printed circuit board, attached to the housing, has a first ground plane and a first power plane. The power pins are electrically coupled to the first power plane and the ground pins are electrically coupled to the first ground plane. The first set of power pins, the second set of ground pins, and the third set of signal pins extend through the printed circuit board.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: July 22, 2003
    Assignee: Intel Corporation
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong
  • Publication number: 20030111264
    Abstract: A shielded test contactor to electrically couple a device to be tested to test circuitry, comprises conductive material covered by or embedded in non-conductive material and defining a well to receive the device. Contacts extend from the embedded conductive material to connect the embedded conductive material to ground. Preferably, the contacts are extensions of the conductive material, through the non-conductive material. A second non-conductive material is preferably provided to support the embedded conductive material and define a floor of the well. Electrical connectors are preferably also supported by the second non-conductive material adjacent to the well, to electrically couple the device to test circuitry. For example, the connectors may be pins supported by the second non-conductive material and extending into the well. Preferably, the height of the conductive material defining the well is at least twice the height of the device to be tested.
    Type: Application
    Filed: December 13, 2001
    Publication date: June 19, 2003
    Inventors: Fern Nee Tan, Suk Yeak Lai, Tark Wooi Fong
  • Publication number: 20020105349
    Abstract: An apparatus for testing electronic devices such as integrated circuits. In one embodiment, an apparatus for testing electronic devices is disclosed that includes a housing such as a test contactor housing which has a plurality of test contactor pins that extend therethrough. The plurality of test contactor pins include a first set of power pins, a second set of ground pins, and a third set of signal pins. A printed circuit board, attached to the housing, has a first ground plane and a first power plane. The power pins are electrically coupled to the first power plane and the ground pins are electrically coupled to the first ground plane. The first set of power pins, the second set of ground pins, and the third set of signal pins extend through the printed circuit board.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 8, 2002
    Inventors: Kok Hong Chan, Chu Aun Lim, Tark Wooi Fong