Abstract: Systems and methods for setting a carrier-sensing mechanism in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a Coexistence InterFrame Space (cEIFS) time period to help the node to avoid interfering with the other technologies. In one embodiment, a PHY primitive is sent from the PHY to the MAC know that there has been a preamble detection. A two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. The MAC sets the carrier-sensing mechanism based on the preamble detection.

Abstract: Methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols. One or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.

Abstract: Embodiments include methods of powerline communications using a preamble with band extension is provided. A method may include receiving a packet data unit PDU. Bit-level repetition is applied to at least a portion of the PDU to create a repeated portion. Interleaving is performed per a subchannel. Pilot tones are inserted in the interleaved portion. Each data tone is modulated with respect to a nearest one of the inserted pilot tones. The PDU is transmitted over a power line.

Abstract: Systems and methods for setting a carrier-sensing mechanism in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a Coexistence InterFrame Space (cEIFS) time period to help the node to avoid interfering with the other technologies. In one embodiment, a PHY primitive is sent from the PHY to the MAC know that there has been a preamble detection. A two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. The MAC sets the carrier-sensing mechanism based on the preamble detection.

Abstract: Methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols. One or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.

Abstract: Embodiments include methods of powerline communications using a preamble with band extension is provided. A method may include receiving a packet data unit PDU. Bit-level repetition is applied to at least a portion of the PDU to create a repeated portion. Interleaving is performed per a subchannel. Pilot tones are inserted in the interleaved portion. Each data tone is modulated with respect to a nearest one of the inserted pilot tones. The PDU is transmitted over a power line.

Abstract: Embodiments of methods and systems for supporting coexistence of multiple technologies in a Power Line Communication (PLC) network are disclosed. A long coexistence preamble sequence may be transmitted by a device that has been forced to back off the PLC channel multiple times. The long coexistence sequence provides a way for the device to request channel access from devices on the channel using other technology. The device may transmit a data packet after transmitting the long coexistence preamble sequence. A network duty cycle time may also be defined as a maximum allowed duration for nodes of the same network to access the channel. When the network duty cycle time occurs, all nodes will back off the channel for a duty cycle extended inter frame space before transmitting again. The long coexistence preamble sequence and the network duty cycle time may be used together.

Abstract: Embodiments of methods and systems for supporting coexistence of multiple technologies in a Power Line Communication (PLC) network are disclosed. A long coexistence preamble sequence may be transmitted by a device that has been forced to back off the PLC channel multiple times. The long coexistence sequence provides a way for the device to request channel access from devices on the channel using other technology. The device may transmit a data packet after transmitting the long coexistence preamble sequence. A network duty cycle time may also be defined as a maximum allowed duration for nodes of the same network to access the channel. When the network duty cycle time occurs, all nodes will back off the channel for a duty cycle extended inter frame space before transmitting again. The long coexistence preamble sequence and the network duty cycle time may be used together.

Abstract: Methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols. One or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.

Abstract: Systems and methods for setting a carrier-sensing mechanism in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a Coexistence InterFrame Space (cEIFS) time period to help the node to avoid interfering with the other technologies. In one embodiment, a PHY primitive is sent from the PHY to the MAC know that there has been a preamble detection. A two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. The MAC sets the carrier-sensing mechanism based on the preamble detection.

Abstract: An electronic device, comprising one or more processors, wherein the one or more processors are configured to execute instructions causing the one or more processors to: receive a machine learning (ML) model and execution information associated with the ML model, wherein the execution information including first execution data indicating how to execute the ML model optimized based on a first performance criterion, and second execution data execution data indicating how to execute the ML model optimized based on a second performance criteria, the second performance criterion different from the first performance criteria; execute the ML model based on the first execution data; determine to execute the ML model based on the second execution data; and execute the ML model based on the second execution data.

Abstract: Methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols. One or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.

Abstract: A method of communicating a packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data payload. The method comprises: (i) first, identifying a quality of a channel between the first node and the second node; (ii) second, in response to the quality of the channel, selecting a manner of communication of the information preceding the data payload; (iii) third, encoding the selected manner of communication in the portion of information preceding data payload; and (iv) fourth, transmitting the packet from the first node to the second node.

Abstract: Systems and methods for setting a carrier-sensing mechanism in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a Coexistence InterFrame Space (cEIFS) time period to help the node to avoid interfering with the other technologies. In one embodiment, a PHY primitive is sent from the PHY to the MAC know that there has been a preamble detection. A two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. The MAC sets the carrier-sensing mechanism based on the preamble detection.

Abstract: In a powerline communications (PLC) network having a first node and at least a second node on a PLC channel utilizing a band including a plurality of tones, based on at least one channel quality indicator (CQI), the first node allocates for a tone map response payload only a single (1) power control bit for each of a plurality of subbands having two or more tones. The power control bit indicates a first power state or a second power state. The first node transmits a frame including the tone map response payload to the second node. The second node transmits a frame having boosted signal power for the tones in the subbands which have the first power state compared to a lower signal power for the tones in the subbands which have the second power state.

Abstract: In a powerline communications (PLC) network having a first node and at least a second node on a PLC channel utilizing a band including a plurality of tones, based on at least one channel quality indicator (CQI), the first node allocates for a tone map response payload only a single (1) power control bit for each of a plurality of subbands having two or more tones. The power control bit indicates a first power state or a second power state. The first node transmits a frame including the tone map response payload to the second node. The second node transmits a frame having boosted signal power for the tones in the subbands which have the first power state compared to a lower signal power for the tones in the subbands which have the second power state.

Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

Abstract: Disclosed examples include heart rate monitor systems and methods to estimate a patient heart rate or rate of another pulsed signal, in which rate hypotheses or states, are identified for a current time window according to digital sample values of the pulsed signal for a current sample time window, and a rate change value is computed for potential rate transitions between states of the current and previous time windows. Transition pair branch metric values are computed as a function of the rate change value and a frequency domain amplitude of the corresponding rate hypothesis for the current time window, and the pulsed signal rate estimate is determined according to a maximum path metric computed according to the branch metric value and a corresponding path metric value for the previous time window.

Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

Abstract: Methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols. One or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.