Abstract: A method in a wireless communication device for diagnosing power supply failure in the wireless communication device is provided. The wireless communication device detects (301) an indication of power supply failure in the wireless communication device. When the indication of the power supply failure further indicates a non-active state of the wireless communication device or when the wireless communication device enters an error handling mode, the wireless communication device collects (302) diagnostic data from the PMU by means of a diagnostic engine (215) in the PMU. The wireless communication device then stores (303) the collected diagnostic data to a memory in the PMU. The data is related to the event resulting in the non-active state and/or to the latest event in a system of the wireless communication device or when the wireless communication device enters an error handling mode.

Abstract: A method of optimizing the number of output stages of a switched mode power supply features a dynamically-updated lookup table (LUT) storing historic output stage configuration data per system operating performance point (OPP). Upon entering an OPP, a margin is added to the historic optimal configuration. During operation at the OPP, the current drawn by the load is periodically monitored, and the number of output stages is dynamically adjusted, as needed (with low pass filtering to ensure stability). When the system exits the OPP, a running average of the optimal number of output stages for the OPP is updated with the actual number of output stages enabled in this iteration of the OPP. A running average of the deviation, or change in number of output stages enabled, is also maintained. The updated values are written to the LUT, for use in setting the initial output stage configuration the next time the same OPP is invoked.

Abstract: A method in a wireless communication device for diagnosing power supply failure in the wireless communication device is provided. The wireless communication device detects (301) an indication of power supply failure in the wireless communication device. When the indication of the power supply failure further indicates a non-active state of the wireless communication device or when the wireless communication device enters an error handling mode, the wireless communication device collects (302) diagnostic data from the PMU by means of a diagnostic engine (215) in the PMU. The wireless communication device then stores (303) the collected diagnostic data to a memory in the PMU. The data is related to the event resulting in the non-active state and/or to the latest event in a system of the wireless communication device or when the wireless communication device enters an error handling mode.

Abstract: A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

Abstract: A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

Abstract: A method of optimizing the number of output stages of a switched mode power supply features a dynamically-updated lookup table (LUT) storing historic output stage configuration data per system operating performance point (OPP). Upon entering an OPP, a margin is added to the historic optimal configuration. During operation at the OPP, the current drawn by the load is periodically monitored, and the number of output stages is dynamically adjusted, as needed (with low pass filtering to ensure stability). When the system exits the OPP, a running average of the optimal number of output stages for the OPP is updated with the actual number of output stages enabled in this iteration of the OPP. A running average of the deviation, or change in number of output stages enabled, is also maintained. The updated values are written to the LUT, for use in setting the initial output stage configuration the next time the same OPP is invoked.

Abstract: A multi-mode I/O circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The I/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors.

Abstract: The invention relates to a mixer circuit 31 comprising a down-conversion mixing component 33 arranged for down-converting an input radio frequency signal Irf+, Irf?. In order to improve such a mixer circuit, it is proposed that it comprises in addition an active mixer load circuit 34 connected to output terminals of the mixing component. The active mixer load circuit includes an active mixer load 51, T1, T2 and modulating means S1-S4 arranged for modulating a flicker noise produced by the active mixer load away from the signal band of a signal Ibb+, Ibb? output by the down-conversion mixing component. The invention relates equally to a receiver, a chip and a device comprising such a mixer circuit and to a method for use with such a mixer circuit.

Abstract: A multi-mode I/O circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The I/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors.

Abstract: A multi-mode I/O circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The I/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors.

Abstract: The invention relates to a mixer circuit 31 comprising a down-conversion mixing component 33 arranged for down-converting an input radio frequency signal Irf+, Irf?. In order to improve such a mixer circuit, it is proposed that it comprises in addition an active mixer load circuit 34 connected to output terminals of the mixing component. The active mixer load circuit includes an active mixer load 51, T1, T2 and modulating means S1-S4 arranged for modulating a flicker noise produced by the active mixer load away from the signal band of a signal Ibb+, Ibb? output by the down-conversion mixing component. The invention relates equally to a receiver, a chip and a device comprising such a mixer circuit and to a method for use with such a mixer circuit.

Abstract: The invention relates to an active current mode sampling circuit comprising an operational amplifier (103) and at least one switched capacitor (C2, C2a, C2b). In order to reduce the power consumption of such a circuit, first switching elements (S101a, S101b, S102a, S102b) switch the switched capacitor (C2, C2a, C2b) between an input and an output of the operational amplifier (103) during charging phases ?1. Further, second switching elements (S103a, S103b, S104a, S104b) connect the switched capacitor (C2, C2a, C2b) during discharging phases ?2 to a subsequent stage (104), in order to provide a charge of the switched capacitor (C2, C2a, C2b) to the subsequent stage (104). The invention relates equally to a device (107) comprising such a sampling circuit and to a method of operating such a sampling circuit.

Abstract: The invention relates to an active current mode sampling circuit comprising an operational amplifier (103) and at least one switched capacitor (C2, C2a, C2b). In order to reduce the power consumption of such a circuit, first switching elements (S101a, S101b, S102a, S102b) switch the switched capacitor (C2, C2a, C2b) between an input and an output of the operational amplifier (103) during charging phases ?1. Further, second switching elements (S103a, S103b, S104a, S104b) connect the switched capacitor (C2, C2a, C2b) during discharging phases ?2 to a subsequent stage (104), in order to provide a charge of the switched capacitor (C2, C2a, C2b) to the subsequent stage (104). The invention relates equally to a device (107) comprising such a sampling circuit and to a method of operating such a sampling circuit.

Abstract: An audio path is constructed to include a multi-bit sigma-delta converter for converting an N-bit digital input to an n-bit output representing an over-sampled, lower resolution n-bit version of the N-bit digital input; a formatter for converting the n-bit output to an m signal output (e.g., as a thermometer code, a SDM format or a PWM format); an m-by-m switching matric for receiving the m output signals and for reordering the m output signals, m class-D drivers individual ones of which are driven by one of the reordered m output signals for driving one of m speakers; and a dynamic element matching (DEM) block coupled to the switching matric for controlling the reordering of the m output signals driving the m class-D drivers for spreading the distortion due at least to driver-speaker pair mismatch to wide band noise. The DEM may operate to generate white noise, or it may generate shaped (colored) noise.

Abstract: An electronic circuit for a switching power amplifier is shown where in order to reduce problems during the transition stage when switching an output stage of the amplifier, the circuit comprises an output stage formed by at least two switching stages 54,55. Each of the switching stages 54,55 comprises at least two power switches and provides an output between the at least two power switches. Further, the switching stages 54,55 are connected in parallel to each other. The proposed circuit comprises in addition clocking means for switching the power switches, wherein the clocking means switch the power switches of at least one of the switching stages 55 in an overlapped mode and the power switches of at least one other of the switching stages 54 in a non-overlapped mode. The invention relates equally to a corresponding method.

Abstract: A sigma-delta modulator (10) has an input node coupled to a first input of a loop filter (12); a quantizer (14) that has an input coupled to an output of the loop filter for receiving a differential input signal therefrom and a feedback path (18) coupled from an output of the quantizer to a second input of the loop filter. The quantizer input includes a first input signal transistor (14A) and a second input signal transistor (14B) having gates coupled to the differential input signal, a first set of transistors (M1a, . . . ,Mna) connected in parallel with the first input signal transistor (M0a), and a second set of transistors (M1b, . . . ,Mnb) connected in parallel with the second input signal transistor (M0b).

Abstract: An electronic circuit for a switching power amplifier is shown where in order to reduce problems during the transition stage when switching an output stage of the amplifier, the circuit comprises an output stage formed by at least two switching stages 54,55. Each of the switching stages 54,55 comprises at least two power switches and provides an output between the at least two power switches. Further, the switching stages 54,55 are connected in parallel to each other. The proposed circuit comprises in addition clocking means for switching the power switches, wherein the clocking means switch the power switches of at least one of the switching stages 55 in an overlapped mode and the power switches of at least one other of the switching stages 54 in a non-overlapped mode. The invention relates equally to a corresponding method.

Abstract: A multimode communications device includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC includes a programmable signal converter core operable to perform ADC functions on a received RF signal in accordance with different types of mobile communication device operational modes, and further includes a multimode control function for programming the signal converter core as a function of a currently selected operational mode. The programmable signal converter core preferably includes a sigma-delta modulator, and a signal analysis function is provided for analyzing the received RF signal for dynamically programming the converter core to adapt to temporary signal and interference conditions by increasing or decreasing the performance of the signal converter.

Abstract: A multi-mode I/O circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The II/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors.

Abstract: A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).