Patents by Inventor Taro Asai

Taro Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8947610
    Abstract: An organic EL display device includes scanning lines, video signal lines, and pixels, each including a TFT having a semiconductor layer and an organic EL layer located between a lower electrode and an upper electrode. A source electrode connecting the semiconductor layer and the lower electrode is formed of three layers including a barrier metal, an Al-containing metal, and a cap metal. The barrier metal is formed of a first layer in contact with the semiconductor layer and a second layer in contact with the Al-containing metal. Each of the first layer, the second layer, and the cap metal is formed of a metal comprising a high melting point metal, and an amount of oxygen in the first layer is larger than an amount of oxygen in the second layer.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 3, 2015
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co. Ltd.
    Inventors: Taro Asai, Jun Gotoh, Eiji Oue, Hiroaki Asuma, Katsumi Nakayashiki, Makoto Kurita
  • Publication number: 20140340606
    Abstract: An organic EL display device includes scanning lines, video signal lines, and pixels, each including a TFT having a semiconductor layer and an organic EL layer located between a lower electrode and an upper electrode. A source electrode connecting the semiconductor layer and the lower electrode is formed of three layers including a barrier metal, an Al-containing metal, and a cap metal. The barrier metal is formed of a first layer in contact with the semiconductor layer and a second layer in contact with the Al-containing metal. Each of the first layer, the second layer, and the cap metal is formed of a metal comprising a high melting point metal, and an amount of oxygen in the first layer is larger than an amount of oxygen in the second layer.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Taro ASAI, Jun GOTOH, Eiji OUE, Hiroaki ASUMA, Katsumi NAKAYASHIKI, Makoto KURITA
  • Patent number: 8817200
    Abstract: A contact resistance in a through-hole with a source or a drain electrode connected to a TFT is decreased, thereby improving the operation efficiency of a display device. In the through-hole, a source portion of the TFT is connected to a source electrode 8. The source electrode 8 is formed of three layers comprising a barrier metal, an Al alloy 82, and a cap metal 83. The barrier metal is divided into a lower layer 81a in contact with the semiconductor layer and an upper layer 81b in contact with the Al alloy. The lower layer 81a of the barrier metal is formed by sputtering, the lower layer 81a is heat-treated and, subsequently, an upper layer 81b of the base metal, the Al alloy 82, and the cap metal 83 are formed continuously by sputtering. Since the upper layer 81b of the barrier metal in contact with the Al alloy 82 is not oxidized, increase in the contact resistance in the through-hole can be prevented.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: August 26, 2014
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Taro Asai, Jun Gotoh, Eiji Oue, Hiroaki Asuma, Katsumi Nakayashiki, Makoto Kurita
  • Publication number: 20110199551
    Abstract: A contact resistance in a through-hole with a source or a drain electrode connected to a TFT is decreased, thereby improving the operation efficiency of a display device. In the through-hole, a source portion of the TFT is connected to a source electrode 8. The source electrode 8 is formed of three layers comprising a barrier metal, an Al alloy 82, and a cap metal 83. The barrier metal is divided into a lower layer 81a in contact with the semiconductor layer and an upper layer 81b in contact with the Al alloy. The lower layer 81a of the barrier metal is formed by sputtering, the lower layer 81a is heat-treated and, subsequently, an upper layer 81b of the base metal, the Al alloy 82, and the cap metal 83 are formed continuously by sputtering. Since the upper layer 81b of the barrier metal in contact with the Al alloy 82 is not oxidized, increase in the contact resistance in the through-hole can be prevented.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 18, 2011
    Inventors: Taro Asai, Jun Gotoh, Eiji Oue, Hiroaki Asuma, Katsumi Nakayashiki, Makoto Kurita
  • Patent number: 7670858
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: March 2, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida
  • Publication number: 20080274576
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Application
    Filed: July 10, 2008
    Publication date: November 6, 2008
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida
  • Patent number: 7411260
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 12, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida
  • Publication number: 20080079099
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Application
    Filed: July 6, 2007
    Publication date: April 3, 2008
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida