Abstract: The invention relates to a thermosetting resin composition which includes a metal filler component, a fluxing component and a thermosetting resin binder. The metal filler component includes at least one of bismuth (Bi) and indium (In), and tin (Sn). The fluxing component, which at least one of a compound of structural formula (1) below and a compound of structural formula (2) below, is used. In the above formulas, R1 to R6 are each a hydrogen or alkyl group, and X is an organic group which has a lone electron pair or double bond ? electrons and is capable of coordinating with a metal.

Abstract: The invention relates to a thermosetting resin composition which includes a metal filler component, a fluxing component and a thermosetting resin binder. The metal filler component includes at least one of bismuth (Bi) and indium (In), and tin (Sn). The fluxing component, which at least one of a compound of structural formula (1) below and a compound of structural formula (2) below, is used. In the above formulas, R1 to R6 are each a hydrogen or alkyl group, and X is an organic group which has a lone electron pair or double bond ? electrons and is capable of coordinating with a metal.

Abstract: The object of the invention is to provide a thermosetting resin composition which, in packaging an electronic circuit containing components incapable of withstanding elevated temperatures, employs low-melting solder particles, thereby enabling batch ref lowing and enabling packaging of components with excellent strength and toughness. The invention relates to a thermosetting resin composition which includes a metal filler component, a fluxing component and a thermosetting resin binder. The metal filler component includes at least one of bismuth (Bi) and indium (In), and tin (Sn). The fluxing component, which at least one of a compound of structural formula (1) below and a compound of structural formula (2) below, is used. In the above formulas, R1 to R6 are each a hydrogen or alkyl group, and X is an organic group which has a lone electron pair or double bond ? electrons and is capable of coordinating with a metal.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Abstract: A process for fabricating a chip package structure is disclosed. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier. The encapsulating material within the bonding gaps has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than half of the said thickness.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier. The encapsulating material within the bonding gaps has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than half of the said thickness.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.

Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.

Abstract: Disclosed is a liquid epoxy resin composition for sealing a semiconductor device which comprises (A) a cyanic acid ester, (B) an epoxy resin, (C) an inorganic filler, (D) a metal chelate and/or a metal salt, and at least one of (E1) an acid anhydride, (E2) a dihydrazide compound and (F) a silicone resin gel, wherein at least one of components A and B is liquid at room temperature, component E1 is liquid at room temperature, and the weight ratio of component C to the total weight of the composition, the weight ratio of component A to component B, and the weight ratio of component E1, E2 or F to the total weight of the composition except component C each ranges a specific ratio.

Abstract: Seal coating mask for semiconductor element and method of use thereof with a seal coating mask with an opening located at a position where a semiconductor element is mounted on a wiring board. The coating mask has an annular protrusion formed along the whole periphery of the opening. A clearance of about 0.01 to 0.5 mm is formed between at least a part of the whole periphery of the annular protrusion and the front surface of the wiring board. The coating mask also includes a space portion formed on the back of the seal coating mask for cutting off cooling material outside of the annular protrusion. The coating mask is used to forcibly coat a material for sealing the semiconductor element in the front surface of the wiring board.

Abstract: An epoxy resin encapsulating material for molding in a semiconductor chip by the use of a transfer molding device. The material has constituents of an epoxy resin, a curing agent, an inorganic filler, and a release agent. The material consists of 99 wt % or more of granules having a diameter of 0.1 to 5.0 mm and 1 wt % or less of minute particles having a diameter of less than 0.1 mm. The mass of the material exhibit an angle of slide of 20 to 40.degree., which demonstrates good flowability free from clogging a passage leading to a mold cavity in the transfer molding device, thereby assuring enhanced encapsulation quality. The material is prepared firstly by kneading the encapsulating composition having the above constituents and by solidifying the composition into a semi-cured solid body of B-stage condition. The sem-cured solid body is then pulverized into pieces having a diameter of 5.0 mm or less. The pieces are composed of granules having a diameter of 0.1 mm to 5.

Abstract: A thermosetting polyimide composition is provided with a sufficient heat resistance and excellent mechanical and electrical characteristics in toughness, flexibility and so on and under severe environmental conditions, by adding to a polyfunctional unsaturated imide a thermosetting resin selected from the group consisting of polyetherimide, polyarylate and polyamideimide which are in a miscibility region with the polyfunctional unsaturated imide and have an excellent glass transition point and a number-average molecular weight of more than 10,000.