Abstract: An adapter is provided which is used when a process for a small-diameter semiconductor substrate (small substrate) is performed by using a semiconductor manufacturing apparatus for large-diameter silicon substrates. The small substrate is attached to an adapter plate that compensates for differences in size, so that the small substrate is prevented from falling even when the small substrate is in a vertical or inverted direction. To process the small substrate with the semiconductor manufacturing apparatus for large-diameter silicon substrates, an opening 10 is formed in a transferring base portion 1, which is formed of a large-diameter silicon substrate, and a polyimide film 2 is attached to the rear surface of the transferring base portion 1, so that the small substrate can be retained by a vacuum chuck or an electrostatic chuck.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer and a semiconductor crystal layer above a semiconductor crystal layer forming wafer, the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer being arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer, wherein the semiconductor wafer comprises a diffusion inhibiting layer that inhibits diffusion of a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer, at any cross-sectional position between (a) the interface of the semiconductor crystal layer forming wafer that faces the sacrificial layer and (b) a middle of the semiconductor crystal layer.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer, a first semiconductor crystal layer, and a second semiconductor crystal layer above a semiconductor crystal layer forming wafer, wherein the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer are arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer, a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer is contained in the first semiconductor crystal layer and the second semiconductor crystal layer as an impurity, and the concentration of the first atom in the second semiconductor crystal layer is lower than the concentration of the first atom in the first semiconductor crystal layer.

Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.

Abstract: Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor.

Abstract: A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.

Abstract: There is provided a method that includes forming a sacrificial layer and the semiconductor crystal layer on a semiconductor crystal layer formation wafer in the stated order, bonding together the semiconductor crystal layer formation wafer and a transfer-destination wafer such that a first surface of the semiconductor crystal layer and a second surface of the transfer-destination wafer face each other, and splitting the transfer-destination wafer from the semiconductor crystal layer formation wafer with the semiconductor crystal layer remaining on the transfer-destination wafer side, by etching away the sacrificial layer by immersing the semiconductor crystal layer formation wafer and the transfer-destination wafer wholly or partially in an etchant. Here, the transfer-destination wafer includes an inflexible wafer and an organic material layer, and a surface of the organic material layer is the second surface.

Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.

Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.

Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.

Abstract: A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.

Abstract: Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor.

Abstract: There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.

Abstract: A resin composition (2) such as a photo-curable resin composition or a heat curable or thermosetting resin composition is placed on an optical substrate (1). A printing pressure is applied to the side of the resin composition (2) of the optical substrate (1) with the resin composition (2) by means of an extra-flat pressing plate having a flatter plane than the optical substrate (1). The resin composition is cured by utilizing light or a temperature change to form a composite substrate. A thin film (4) such as a functional inorganic optical film, a dielectric multilayered optical thin film, or an optical functional metallic film is stacked on the composite substrate, for example, by low-temperature sputtering or ion beam sputtering to form an optical component such as a reflection mirror, a beam splitter, a band-pass filter, a band-stop filter, and an edge filter.

Abstract: In the detection of fluorescence Lf emitted by a micro-object irradiated with an excitation light Le by a semiconductor light-detecting element 20, a converging microlens 62 for converging the excitation light Le elevating the optical density thereof and irradiating the micro-object with the light, causing the micro-object to generate fluorescence Lf due to two-photon absorption, is inserted partway along the light path of the excitation light Le. This enables the fluorescence Lf emitted by the micro-object to be detected with high sensitivity.

Abstract: An electric signal transmission line includes a signal electrode portion, a ground electrode portion and a dielectric portion formed on a semiconductor substrate. The signal electrode portion has a metal electrode through which an electric signals flows. The ground electrode portion has a grounded metal electrode. The metal electrode of the signal electrode portion and the metal electrode of the ground electrode portion are connected with a semiconductor PN junction. The dielectric portion is formed by using a dielectric to cover a region between the metal electrode of the signal electrode portion and the metal electrode of the ground electrode portion through which a line of electric force runs and is a region in which energy of transmitted electric signals exist.

Abstract: An electric signal transmission line includes a signal electrode portion (2), a ground electrode portion (3) and a dielectric portion (4) formed on a semiconductor substrate (1). The signal electrode portion (2) has a metal electrode (21) through which the electric signals flow, an upper conductive semiconductor (22) and a lower conductive semiconductor (23). The ground electrode portion (3) has a grounded metal electrode (31) and a conductive semiconductor (32). With the upper conductive semiconductor (22) and lower conductive semiconductor (23) having opposite polarities, the metal electrode (21) of the signal electrode portion 2 and the metal electrode (31) of the ground electrode portion (3) are connected with a semiconductor PN junction. A dielectric material fills and covers a region between the metal electrode (21) of the signal electrode portion (2) and the metal electrode (31) of the ground electrode portion (3) through which a line of electric force runs to form the dielectric portion (4).

Abstract: In the detection of fluorescence Lf emitted by a micro-object irradiated with an excitation light Le by a semiconductor light-detecting element 20, a converging microlens 62 for converging the excitation light Le elevating the optical density thereof and irradiating the micro-object with the light, causing the micro-object to generate fluorescence Lf due to two-photon absorption, is inserted partway along the light path of the excitation light Le. This enables the fluorescence Lf emitted by the micro-object to be detected with high sensitivity.

Abstract: When amounts of change in shape of a plurality of deforming portions of the deformable mirror are adjusted, the deformable mirror including: a mirror surface in which the plurality of deforming portions are set and changes in shape of the deforming portions have influence on one another; and a plurality of deforming means for changing shapes of the plurality of deforming portions of the mirror surface respectively in response to control signals from the outside, and the deformable mirror changing a three-dimensional shape of the mirror surface in a segment-to-segment basis in a way that the deforming means change the shapes of the deforming portions of the mirror surface, reflected light, which has been outputted from a predetermined light source, and which has been reflected by the mirror surface, is detected at a predetermined position; the detected, reflected light is evaluated in accordance with a predetermined criteria; and the amounts of change in shape of the plurality of deforming portions are adjuste

Abstract: An optical apparatus has an adjustment apparatus 5 and an optical unit 1 including a plurality of optical elements. The adjustment apparatus sequentially provides control signals that, according to a probabilistic search technique, change the parameters of a stipulated plurality of optical elements among the optical elements to become parameters that cause the functions of the optical apparatus to satisfy stipulated specifications. A method of adjusting the optical apparatus includes sequentially providing control signals that, according to a probabilistic search technique, change the parameters of the stipulated plurality of optical elements among the optical elements, and searching for optical values at which the functions of the optical apparatus the stipulated specification.