Abstract: A memory system includes a nonvolatile memory and a memory controller including a bus, a cache memory, a direct memory access controller, a first search circuit, a second search circuit, and a transfer control circuit. The direct memory access controller transfers cache target data stored in the nonvolatile memory to the cache memory. The second search circuit searches the cache target data that is being transferred. The transfer control circuit assigns, in response to the second search circuit detecting a search hit, to the transfer control circuit and the second search circuit, a bus right which has been assigned at least to the cache memory for the transfer of the cache target data to the cache memory, and obtains, by using the assigned bus right, a search result from the second search circuit via the bus.

Abstract: A memory system includes a nonvolatile memory, and a memory controller configured to control the nonvolatile memory. The nonvolatile memory stores a busy table. The memory controller loads the busy table and controls a chip enable signal for the nonvolatile memory based on the busy table.

Abstract: A memory system includes a nonvolatile memory, and a memory controller configured to control the nonvolatile memory. The nonvolatile memory stores a busy table. The memory controller loads the busy table and controls a chip enable signal for the nonvolatile memory based on the busy table.

Abstract: According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes.

Abstract: According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes.

Abstract: A memory controller includes a processor that includes a monitoring module, a control module, and a parity generating module. The monitoring module receives a data sequence and checks the data sequence for a designated pattern. The control module determines page size of data sequences that include the designated pattern and arranges an idle area for each page based on the total data quantity and the size of the data sequence, where the data quantity of the data stored in each page is uniform. The parity generating module generates the extended parity in the idle area based on a portion of the data stored in each page and the management information of the page. In each page, the control module stores a portion of the data and the extended parity in the idle area.

Abstract: According to one embodiment, a memory system includes a storage unit including a buffer and a nonvolatile first memory, and a first controller which includes a processor and a volatile second memory, and in which the processor controls the storage unit based on data stored in the second memory, and issues a first command when switching from a normal state to a standby state. The memory system also includes a second controller which issues a second command for reading data from the first memory to the buffer, based on the first command, and issues a third command for reading the data from the buffer and storing the data in the second memory, when the first controller switches from the standby state to the normal state.