Abstract: A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.

Abstract: A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.