Patents by Inventor Taro Muraki

Taro Muraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11838660
    Abstract: Since a failure related to an output from a sensor is not detected from an image signal and a failure of the sensor is not detected from an output from the sensor in a system including the sensor for abnormality detection, it is not possible to perform the abnormality detection and to indicate the abnormality to the outside of the system. An apparatus includes a pixel area including multiple pixels, multiple sensors, a processing unit that compares signals based on outputs from the multiple sensors with each other, an output unit that outputs information based on a result of comparison.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: December 5, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Tatsuya Ryoki, Yu Arishima, Taro Muraki
  • Patent number: 11824532
    Abstract: A level shift circuit includes: a first transistor connected to ground and having a control terminal; a second transistor connected to the ground and having a control terminal connected to the a terminal of the first transistor; a pull-up circuit connected to a power source and also connected to the first terminal of the first transistor, and having a current mirror circuit constituted by two transistors; a third transistor having a first terminal connected to the first terminal of the first transistor, a second terminal connected to the power source, and a control terminal connected to a first terminal of the second transistor; and a fourth transistor having a first terminal connected to the first terminal of the second transistor, a second terminal connected to the power source, and a control terminal connected to the first terminal of the first transistor.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: November 21, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taro Muraki, Naoki Isoda
  • Publication number: 20230101695
    Abstract: A level shift circuit includes: a first transistor connected to ground and having a control terminal; a second transistor connected to the ground and having a control terminal connected to the a terminal of the first transistor; a pull-up circuit connected to a power source and also connected to the first terminal of the first transistor, and having a current mirror circuit constituted by two transistors; a third transistor having a first terminal connected to the first terminal of the first transistor, a second terminal connected to the power source, and a control terminal connected to a first terminal of the second transistor; and a fourth transistor having a first terminal connected to the first terminal of the second transistor, a second terminal connected to the power source, and a control terminal connected to the first terminal of the first transistor.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 30, 2023
    Inventors: Taro Muraki, Naoki Isoda
  • Publication number: 20220247947
    Abstract: Since a failure related to an output from a sensor is not detected from an image signal and a failure of the sensor is not detected from an output from the sensor in a system including the sensor for abnormality detection, it is not possible to perform the abnormality detection and to indicate the abnormality to the outside of the system. An apparatus includes a pixel area including multiple pixels, multiple sensors, a processing unit that compares signals based on outputs from the multiple sensors with each other, an output unit that outputs information based on a result of comparison.
    Type: Application
    Filed: January 27, 2022
    Publication date: August 4, 2022
    Inventors: Tetsuya Itano, Tatsuya Ryoki, Yu Arishima, Taro Muraki
  • Publication number: 20160300915
    Abstract: A substrate 1 having metal layers 2A and 2B arranged to form a gap is dipped in an electroless plating solution mixed an electrolyte solution including metal ions with a reducing agent and a surfactant. Metal ions are reduced by the reducing agent to be precipitated on the metal layers 2A and 2B, and the surfactant is adhered to a surface of the metal on the metal layers, thereby forming a pair of electrodes 4A, 4B to be controlled to have a nanometer sized gap. These steps enable to provide a method for fabricating nanogap electrodes, a nanogap electrodes array, and a nanodevice with the same.
    Type: Application
    Filed: March 14, 2016
    Publication date: October 13, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Taro Muraki, Daisuke Tanaka
  • Publication number: 20140054788
    Abstract: A substrate 1 having metal layers 2A and 2B arranged to form a gap is dipped in an electroless plating solution mixed an electrolyte solution including metal ions with a reducing agent and a surfactant. Metal ions are reduced by the reducing agent to be precipitated on the metal layers 2A and 2B, and the surfactant is adhered to a surface of the metal on the metal layers, thereby forming a pair of electrodes 4A, 4B to be controlled to have a nanometer sized gap. These steps enable to provide a method for fabricating nanogap electrodes, a nanogap electrodes array, and a nanodevice with the same.
    Type: Application
    Filed: February 28, 2012
    Publication date: February 27, 2014
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Taro Muraki, Daisuke Tanaka
  • Publication number: 20090044882
    Abstract: The invention provides an oil well pipe for expandable tubular applications excellent in post-expansion toughness and a method of manufacturing the oil well pipe. The oil well pipe for expandable tubular applications comprises, in mass %, C: 0.03 to 0.14%, Si: 0.8% or less, Mn: 0.3 to 2.5%, P: 0.03% or less, S: 0.01% or less, Ti: 0.005 to 0.03%, Al: 0.1% or less, N: 0.001 to 0.01%, B: 0.0005 to 0.003%, optionally comprises one or move of Nb, Ni, Mo, Cr, Cu and V, and further optionally comprises one or both of Ca and REM, satisfies the relationship A=2.7C+0.4Si+Mn+0.45Ni+0.45Cu+0.8Cr+2Mo?1.8, has a balance of iron and unavoidable impurities, and is formed of tempered martensite structure. The manufacturing method according to the invention is characterized in subjecting a steel stock pipe of the foregoing composition to hardening from a temperature range of Ac3 point+30° C. or greater and to tempering at a temperature of 350 to 720° C.
    Type: Application
    Filed: June 9, 2006
    Publication date: February 19, 2009
    Inventors: Hitoshi Asahi, Taro Muraki, Hideyuki Nakamura, Eiji Tsuru
  • Patent number: 6551920
    Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: April 22, 2003
    Assignee: United Microelectronics Corporation
    Inventors: Tomoyuki Uchiyama, Kazuhisa Sasaki, Taro Muraki
  • Publication number: 20020079586
    Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.
    Type: Application
    Filed: February 26, 2002
    Publication date: June 27, 2002
    Applicant: NIPPON STEEL CORPORATION
    Inventors: Tomoyuki Uchiyama, Kazuhisa Sasaki, Taro Muraki
  • Patent number: 6406564
    Abstract: This invention provides a boiler steel pipe that exhibits a high creep rupture strength on a high-temperature high-pressure side and is excellent in electric weldability, and an electric welded boiler steel pipe having fewer defects at an electric welded portion. The boiler steel contains, in terms of wt %, C: 0.01 to 0.20%, Si: 0.01 to 1.0% and Mn: 0.10 to 2.0%, contains further Cr: 0.5 to 3.5%, and limits p≦0.030%, S≦0.010% and 0≦0.20%, wherein a weight ratio of (Si %)/(Mn %) or (Si %)/(Mn %+Cr %) is from 0.005 to 1.5, the balance Fe and unavoidable impurities, and the melting point of the mixed oxide of SiO2 and MnO, or SiO2, MnO and Cr2O3, is not higher than 1,600° C. The oxide that would otherwise result in the defects of the electric welded portion is molten and squeezed out as slag components.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: June 18, 2002
    Assignee: Nippon Steel Corporation
    Inventors: Taro Muraki, Yasushi Hasegawa, Junichi Okamoto
  • Patent number: 6372630
    Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: April 16, 2002
    Assignee: Nippon Steel Corporation
    Inventors: Tomoyuki Uchiyama, Kazuhisa Sasaki, Taro Muraki
  • Patent number: 6162307
    Abstract: This invention provides a ferritic heat-resistant steel that can improve HAZ softening resistance, can omit heat-treatment after welding and can reduce the construction cost of a power generation plant. This ferritic heat-resistant steel contains C: 0.01 to 0.06%, Si: 0.02 to 0.80%, Mn: 0.20 to 1.50%, Cr: 0.50 to 3.00%, Mo: 0.01 to 1.50%, W: 0.01 to 3.50%, V: 0.02 to 1.00%, Nb: 0.01 to 0.50%, N: 0.001 to 0.06%, B: 0.0003 to 0.008%, Ti: 0.001 to 0.5%, Zr: 0.001 to 0.5%, or containing one of Cu: 0.1 to 2.0%, Ni: 0.1 to 2.0% and Co: 0.1 to 2.0% either individually or in combination, and limiting P to not greater than 0.030%, S to not greater than 0.010% and O to not greater than 0.020%, wherein a weight ratio of TiN and BN in the steel is controlled to 1 to 100 in terms of a value (TiN+ZrN %)/(BN %), and a mean grain diameter of BN is not greater than 1 .mu.m.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: December 19, 2000
    Assignee: Nippon Steel Corporation
    Inventors: Yasushi Hasegawa, Taro Muraki
  • Patent number: 5716465
    Abstract: A high-corrosion-resistant martensitic stainless steel possessing excellent weldability and SSC resistance, having a tempered martensitic structure, characterized by comprising steel constituents satisfying by weight C: 0.005 to 0.035%, Si: not more than 0.50%, Mn: 0.1 to 1.0%, P: not more than 0.03%, S: not more than 0.005%, Mo: 1.0 to 3.0%, Cu: 1.0 to 4.0%, Ni: 1.5 to 5.0%, Al: not more than 0.06%, N: not more than 0.01%, and Cr satisfying a requirement represented by the formula 13>Cr+1.6Mo.gtoreq.8,C+N.gtoreq.0.03,40C+34N+Ni+0.3Cu-1.1Cr-1.8 Mo.gtoreq.10,or further comprising at least one element selected from the group consisting of Ti: 0.05 to 0.1%, Zr: 0.01 to 0.2%, Ca: 0.001 to 0.02%, and REM: 0.003 to 0.4%, with the balance consisting essentially of Fe. A process for producing a martensitic stainless steel, comprising the steps of: subjecting a steel plate, produced by hot-rolling a stainless steel slab having the above composition, to austenitization at a temperature of Ac.sub.3 point to 1000.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: February 10, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Takuya Hara, Asahi Hitoshi, Hiroshi Tamehiro, Taro Muraki, Akira Kawakami