Abstract: According to one embodiment, a PLL circuit generates a first signal of 1/m times from a reference clock and a second signal of 1/n times from an output of an oscillator, obtains a quantized phase difference corresponding to a shift amount between the both signals, integrates the phase difference, predicts a control value for the oscillator based on the integrated value, converts the predicted control value into an analog value. Sequential integration is performed for the phase difference until the polarity of the phase difference is reversed from negative to positive and then from positive to negative again, or until the polarity is reversed from positive to negative and then from negative to positive again, a predictive weight value is generated by multiplying the integrated value by a predictive coefficient value of optional ratio, and the control value is obtained by adding the predictive weight value to the integrated value.

Abstract: According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator unit and a processing unit. The level reduction unit reduces an input digital signal to generate a level-reduced signal. The first buffer gate unit generates a first output signal. The first output signal has first or second level if the digital signal is or is not higher than a preset threshold level, respectively. The second buffer gate unit generates a second output signal. The second output signal has the first or second level if the level-reduced signal is or is not higher than the preset threshold level, respectively. The comparator unit compares the first and second output signals to generate a comparison result. The processing unit determines whether a malfunction will soon occur, based on the comparison result.

Abstract: According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator unit and a processing unit. The level reduction unit reduces an input digital signal to generate a level-reduced signal. The first buffer gate unit generates a first output signal. The first output signal has first or second level if the digital signal is or is not higher than a preset threshold level, respectively. The second buffer gate unit generates a second output signal. The second output signal has the first or second level if the level-reduced signal is or is not higher than the preset threshold level, respectively. The comparator unit compares the first and second output signals to generate a comparison result. The processing unit determines whether a malfunction will soon occur, based on the comparison result.

Abstract: According to one embodiment, a PLL circuit generates a first signal of 1/m times from a reference clock and a second signal of 1/n times from an output of an oscillator, obtains a quantized phase difference corresponding to a shift amount between the both signals, integrates the phase difference, predicts a control value for the oscillator based on the integrated value, converts the predicted control value into an analog value. Sequential integration is performed for the phase difference until the polarity of the phase difference is reversed from negative to positive and then from positive to negative again, or until the polarity is reversed from positive to negative and then from negative to positive again, a predictive weight value is generated by multiplying the integrated value by a predictive coefficient value of optional ratio, and the control value is obtained by adding the predictive weight value to the integrated value.

Abstract: If the number of frame synchronization protecting stages for the transmission signal is m (m is a natural number) and the number of protecting stages for the state notice information is n (n is a natural number), when the expression n?m<n×2 holds, the contents shown in the state notice information corresponding to a k-th stage (where k is a natural number fulfilling the expressing m<k?n×2) frame using time X as a reference are regarded as valid among the contents shown in the state notice information protected over n stages using time X as a reference. Here, time X is the time when Out of Frame occurred.

Abstract: Wavelength-multiplexed light including wavelength lights is separated at periodic intervals of wavelength by means of a periodic optical filter, thereby generating wavelength groups composed of the following wavelength lights. Then, an optical switching section selects any one of the wavelength groups and introduces the selected wavelength group into a periodic optical filter. Making the period p of the periodic optical filter different from the period q of the periodic optical filter causes the wavelength lights included in each wavelength group to be outputted at the different separation ports of the periodic optical filter. As a result, each wavelength light is separated completely from the other wavelength lights.

Abstract: If the number of frame synchronization protecting stages for the transmission signal is m (m is a natural number) and the number of protecting stages for the state notice information is n (n is a natural number), when the expression n≦m<n×2 holds, the contents shown in the state notice information corresponding to a k-th stage (where k is a natural number fulfilling the expressing m<k<n×2) frame using time X as a reference are regarded as valid among the contents shown in the state notice information protected over n stages using time X as a reference. Here, time X is the time when Out of Frame occurred.

Abstract: A block processing section divides message data into a plurality of blocks, so as to obtain a plurality of data blocks. A plurality of data encryption processing sections are provided in correspondence to the data blocks. The first one of the data encryption processing sections selects one of pre-stored data conversion algorithms in response to an initial selection control signal. Each of the remaining data encryption processing sections selects one of the data conversion algorithms in response to a selection control signal supplied from a preceding data encryption processing section. Each of the data encryption processing sections performs data encryption processing with respect to the corresponding data block on the basis of the selected data conversion algorithm, and generates a selection control signal to be supplied to the succeeding data encryption processing section, on the basis of the data obtained by the data encryption processing.

Abstract: A block processing section divides message data into a plurality of blocks, so as to obtain a plurality of data blocks. A plurality of data encryption processing sections are provided in correspondence to the data blocks. The first one of the data encryption processing sections selects one of pre-stored data conversion algorithms in response to an initial selection control signal. Each of the remaining data encryption processing sections selects one of the data conversion algorithms in response to a selection control signal supplied from a preceding data encryption processing section. Each of the data encryption processing sections performs data encryption processing with respect to the corresponding data block on the basis of the selected data conversion algorithm, and generates a selection control signal to be supplied to the succeeding data encryption processing section, on the basis of the data obtained by the data encryption processing.

Abstract: A sharp phase variation of a clock is suppressed when master/slave status of a first and second communication device is changed over. The first and second communication devices respectively include clock selection circuits and clock production circuits for producing a synchronous clock from the selected clock, respectively, and supply the selected clock as the synchronous clock to the other communication device which is a mating-side device. One of the first and the second communication devices is a reference selection side and becomes a slave side, and the other device is a mating synchronous clock selection side and becomes a master side. Respective data signals from the communication devices are bit multiplexed in a multiplexing device on the basis of the synchronous clock.

Abstract: A block processing section divides message data into a plurality of blocks, so as to obtain a plurality of data blocks. A plurality of data encryption processing sections are provided in correspondence to the data blocks. The first one of the data encryption processing sections selects one of pre-stored data conversion algorithms in response to an initial selection control signal. Each of the remaining data encryption processing sections selects one of the data conversion algorithms in response to a selection control signal supplied from a preceding data encryption processing section. Each of the data encryption processing sections performs data encryption processing with respect to the corresponding data block on the basis of the selected data conversion algorithm, and generates a selection control signal to be supplied to the succeeding data encryption processing section, on the basis of the data obtained by the data encryption processing.

Abstract: A digital signal exchange equipment is disclosed which is constructed of a combination of selector modules each constituted by a plurality of gate arrays as a parallel unit in a column direction. The respective gate array comprises a first gate for selecting one line from an n number of first input lines and connecting it to an output line, a second gate for selecting one line from an output line of the first gate and one second input line and connecting it to the second gate and a flip-flop for wave-shaping an output of the second gate and, at the same time, taking synchronization among the respective gate array. The selector module as set forth above is constructed of a semiconductor circuit device. When, in particular, a plurality of selector modules are combined together, they are arranged as a k-column/l-row array in which input bus lines are each connected to each common row and an n number of output lines are connected for each row to an n number of second input lines of the next-row selector module.

Abstract: In a signal distribution system, a bus transmission path is provided on which at least one terminal of a pair of transmission lines terminates in a proper potential through a line-to-ground characteristic impedance Z.sub.0. A pair of differential output terminals of at least one transmission circuit are connected to the corresponding pair of transmission lines on the bus transmission path to deliver differential transmission signals of a fundamental frequency f as output signals. A pair of differential input terminals of a respective one of a maximal number of reception circuits, N, are connected to the corresponding pair of transmission lines through a corresponding pair of branch resistors. The input terminal of the respective reception circuit has a characteristic of an input impedance Z.sub.L given below:Z.sub.L =R.sub.L +1/j2.pi.fC.sub.Lwhere R.sub.L and C.sub.L represent an effective resistive component and capacitive component, respectively, of the reception circuit. Here the values R.sub.1, R.sub.

Abstract: A signal wiring board of the present invention includes a dielectric layer and a signal transmission path formed on a surface opposite to a surface of a ground layer formation surface on the board. The signal transmission path is composed of a pair of differential transmission lines which in turn is formed of a microstrip. Differential signals of opposite polarities are transmitted through the paired transmission lines on the signal transmission path such that electric currents of opposite senses flow through the paired differential transmission lines, respectively. With the electric currents there being a positive and a negative polarity, electric lines of force are also created between the transmission lines. The electric lines of force are strengthened as a gap G becomes narrower.

Abstract: A signal conversion circuit is used to convert a parallel signal to a serial signal and comprises a parallel input/serial output type of shift register having input terminals corresponding in number to at least n+k bits (n and k: integer), an inverting circuit and a timing circuit. The n-bit input parallel signal is applied to n successive input terminals of the shift register and k bit of the n-bit parallel signal is inverted by the inverting circuit to be applied to the remaining k input terminal of the shift register. The (n+k)-bit parallel signal loaded into the shift register is serially output at a predetermined rate by the timing circuit to provide a serial signal.

Abstract: In the pulsed FM system, the input signal is first modulated into the pulse FM signal. Thereafter, this pulse FM signal is modulated into the pulsed FM signal by the frequency divider. This pulsed FM system is suitable to CATV.

Abstract: N framing units block N-channel input digital signals, respectively, to provide blocked signals. The framing units respond to a common block synchronization signal from a multiplexing unit to provide the blocked signals in a time relation suitable for multiplexing. The multiplexing unit multiplexes the blocked signals from the framing units to provide a multiplexed signal (higher-order group signal).

Abstract: This invention provides a zero signal state detecting circuit for detecting zero signal state of the signal in an optical receiver or optical repeater. The zero signal state detecting circuit in accordance with the present invention comprises a level shifting circuit, a smoothing circuit, a first comparator, a peak detecting circuit and a second comparator. The output signal from the timing circuit to produce two output signals is shifted by the level shifting circuit. One of the two outputs of the level shifting circuit is smoothed by the smoothing circuit. The output of the smoothing circuit and the other one of the outputs of the level shifting circuit are compared by the first comparator and the output is detected by the peak detecting circuit. The output of the peak detecting circuit is compared by the second comparator against a reference voltage, and the zero signal state of the optical receiving signal is detected.

Abstract: A drive circuit supplies a semiconductor laser with current pulses corresponding to an input pulse signal. A current supply feeds a d.c. bias current to the laser. A monitoring photodiode produces a light detection signal indicative of the actual laser output level. The detection signal is supplied to a subtraction device, to which the pulse signal is also supplied via a low-pass filter. The subtraction device detects the difference between the two signals to produce an error signal. Integration devices produce average value signals, which are compared by comparators with reference voltages to obtain control signals. The current supply and the current drive circuit are responsive to these control signals to independently modulate the d.c. bias current and the amplitude of the drive pulses applied to the laser, whereby the laser output level can be stabilized to remain at a constant level.

Abstract: In this information transmission system, a PCM encoder is provided for time-division multiplexing multichannel audio signals and a digital character information signal to generate a time-division multiplexed, or TDM, information signal. The TDM information signal is angle-modulated by the modulator to generate an angle-modulated information signal. This signal is supplied to a frequency-division multiplexer, which multiplexes the angle-modulated information signal and an image signal so as to generate a frequency-division multiplexed, or FDM, information signal which is adapted to be supplied to a certain subscriber.