Patents by Inventor Taro SHIOKAWA
Taro SHIOKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240057313Abstract: A semiconductor device includes a semiconductor substrate, a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film, a second layer formed above the first layer and including a channel including an oxide semiconductor and a second insulating film, and a third layer formed above the second layer, and including an electrode formed on the channel and a third insulating film having a film density less than at least one of a film density of the first insulating film or a film density of the second insulating film.Type: ApplicationFiled: March 7, 2023Publication date: February 15, 2024Applicant: Kioxia CorporationInventors: Taro SHIOKAWA, Takeru MAEDA, Kotaro NODA, Shosuke FUJII
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Patent number: 11871557Abstract: A semiconductor device according to the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode and having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer.Type: GrantFiled: March 9, 2022Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Taro Shiokawa, Kiwamu Sakuma, Keiko Sakuma
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Publication number: 20230328957Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode surrounding the oxide semiconductor layer; and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, spaced from the first electrode, and containing nitrogen (N). In addition, a first distance between the first electrode and the gate insulating layer in a first direction from the first electrode to the second electrode is smaller than a second distance between the first electrode and the gate electrode in the first direction.Type: ApplicationFiled: September 2, 2022Publication date: October 12, 2023Applicant: Kioxia CorporationInventors: Masaya TODA, Tomoki ISHIMARU, Ha HOANG, Kota TAKAHASHI, Kazuhiro MATSUO, Takafumi OCHIAI, Shoji HONDA, Kenichiro TORATANI, Kiwamu SAKUMA, Taro SHIOKAWA, Mutsumi OKAJIMA
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Publication number: 20230299206Abstract: A semiconductor device includes: a first electrode; a second electrode; a first oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode around the first oxide semiconductor layer; a second oxide semiconductor layer provided between the gate electrode and the first oxide semiconductor layer, and separated from the first electrode; and a gate insulating layer provided between the gate electrode and the second oxide semiconductor layer.Type: ApplicationFiled: August 31, 2022Publication date: September 21, 2023Applicant: Kioxia CorporationInventors: Keiko SAKUMA, Taro SHIOKAWA, Kiwamu SAKUMA
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Publication number: 20230197857Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer between the first electrode and the second electrode and including a first region surrounded by the first electrode in a plane perpendicular to a first direction from the first electrode toward the second electrode; a gate electrode facing the oxide semiconductor layer; a gate insulating layer; a first insulating layer between the gate electrode and the first electrode; and a second insulating layer between the gate electrode and the second electrode. A first maximum distance between a first portion of the first electrode and a second portion of the first electrode in a second direction in a cross section parallel to the first direction is larger than a minimum distance between a third portion of the first insulating layer and a fourth portion of the first insulating layer in the second direction.Type: ApplicationFiled: June 16, 2022Publication date: June 22, 2023Applicant: Kioxia CorporationInventors: Taro SHIOKAWA, Kiwamu SAKUMA, Keiko SAKUMA, Mutsumi OKAJIMA, Kazuhiro MATSUO, Masaya TODA
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Publication number: 20230103593Abstract: A transistor includes an upper electrode; a lower electrode; a gate electrode disposed between the upper electrode and the lower electrode; and a columnar portion penetrating the gate electrode and provided between the upper electrode and the lower electrode. The columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode. The semiconductor layer is embedded in the tubular gate insulating film and between the gate insulating film and the upper electrode and in contact with the upper electrode.Type: ApplicationFiled: March 3, 2022Publication date: April 6, 2023Inventors: Kiwamu SAKUMA, Taro SHIOKAWA, Keiko SAKUMA
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Publication number: 20230088455Abstract: A semiconductor device according to the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode and having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer.Type: ApplicationFiled: March 9, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Taro Shiokawa, Kiwamu Sakuma, Keiko Sakuma
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Patent number: 11506536Abstract: According to one embodiment, there is provided a measuring apparatus including a measurement section and a control section. The measurement section is configured to acquire a response from a sample. The control section is configured to compare a loading obtained by performing principal component analysis in advance with a first evaluation-use loading obtained by performing principal component analysis onto the response acquired from the sample, and to generate a first reliability index for measurement using principal component analysis, in accordance with a comparison result.Type: GrantFiled: September 5, 2019Date of Patent: November 22, 2022Assignee: Kioxia CorporationInventor: Taro Shiokawa
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Publication number: 20220302169Abstract: A semiconductor storage device includes a channel layer extending along a first direction and including titanium oxide, an electrode layer extending along a second direction crossing the first direction, and a ferroelectric layer between the channel layer and the electrode layer and including titanium.Type: ApplicationFiled: August 25, 2021Publication date: September 22, 2022Inventors: Keisuke TAKAGI, Kazuhiro MATSUO, Kunifumi SUZUKI, Yuuichi KAMIMUTA, Taro SHIOKAWA, Masumi SAITOH, Yuta KAMIYA, Kota TAKAHASHI
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Patent number: 11195855Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor.Type: GrantFiled: February 19, 2020Date of Patent: December 7, 2021Assignee: Kioxia CorporationInventors: Kenichi Kadota, Kazuhiro Nojima, Taro Shiokawa
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Patent number: 10943919Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.Type: GrantFiled: August 2, 2019Date of Patent: March 9, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shigeki Kobayashi, Taro Shiokawa, Masahisa Sonoda
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Publication number: 20210066339Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first interconnect layers including first and second conductors; a second interconnect layer arranged above the first interconnect layers; a third interconnect layer arranged adjacently to the second interconnect layer; a first pillar passing through the first interconnect layers and the second interconnect layer; a second pillar passing through the first interconnect layers and the third interconnect layer; and a third pillar arranged between the second interconnect layer and the third interconnect layer and passing through the first interconnect layers. The second conductor covers a top surface and a bottom surface of the first conductor, and a side surface of an end portion of the first conductor.Type: ApplicationFiled: February 19, 2020Publication date: March 4, 2021Applicant: Kioxia CorporationInventors: Kenichi Kadota, Kazuhiro Nojima, Taro Shiokawa
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Publication number: 20200303402Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.Type: ApplicationFiled: August 2, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shigeki KOBAYASHI, Taro SHIOKAWA, Masahisa SONODA
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Publication number: 20200292387Abstract: According to one embodiment, there is provided a measuring apparatus including a measurement section and a control section. The measurement section is configured to acquire a response from a sample. The control section is configured to compare a loading obtained by performing principal component analysis in advance with a first evaluation-use loading obtained by performing principal component analysis onto the response acquired from the sample, and to generate a first reliability index for measurement using principal component analysis, in accordance with a comparison result.Type: ApplicationFiled: September 5, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Taro SHIOKAWA
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Patent number: 10748915Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.Type: GrantFiled: March 1, 2018Date of Patent: August 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuhiro Nojima, Megumi Shibata, Tomonori Kajino, Taro Shiokawa
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Publication number: 20190081053Abstract: According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.Type: ApplicationFiled: March 1, 2018Publication date: March 14, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kazuhiro NOJIMA, Megumi SHIBATA, Tomonori KAJINO, Taro SHIOKAWA