Patents by Inventor Taro Yamasaki
Taro Yamasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200256755Abstract: A parasitic ribbon sensor includes: a first conductive line including a first metal portion formed of a first metal; and a second conductive line including a second metal portion formed of a second metal being different from the first metal, the second conductive line being placed parallel to the first conductive line, being shaped in a ribbon shape together with the first conductive line.Type: ApplicationFiled: February 10, 2020Publication date: August 13, 2020Inventors: Yoshihide WAKAYAMA, Teruo YAMAMIYA, Takashi HASEBE, Shozo NISHIYAMA, Toshihiko UEDA, Yusuke TAKEUCHI, Taro YAMASAKI, Norihiro OKAZAKI, Fumiyasu UTSUNOMIYA, Ryo YAMAMURA, Kouichi TAKAHASHI
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Patent number: 10504359Abstract: There is provided a wireless control system which has a node apparatus including a power generating device, a capacitor and a voltage conversion circuit device connected to the power generating device, and a wireless device having a transmitter function, and connected to the voltage conversion circuit device; a gateway device having a transceiver function of transmitting and receiving a wireless signal transmitted from the node apparatus; and a server device connected to the gateway device, and further has a receiving device which receives a signal transmitted from the gateway device having the transceiver function, and an actuator operated by a signal sent from the receiving device, and in which power with which the node apparatus operates is supplied from the power generating device, and the power generated in the power generating device is increased and decreased by the actuator.Type: GrantFiled: September 28, 2018Date of Patent: December 10, 2019Assignee: ABLIC INC.Inventors: Sadashi Shimoda, Yusuke Takeuchi, Taro Yamasaki
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Publication number: 20190103015Abstract: There is provided a wireless control system which has a node apparatus including a power generating device, a capacitor and a voltage conversion circuit device connected to the power generating device, and a wireless device having a transmitter function, and connected to the voltage conversion circuit device; a gateway device having a transceiver function of transmitting and receiving a wireless signal transmitted from the node apparatus; and a server device connected to the gateway device, and further has a receiving device which receives a signal transmitted from the gateway device having the transceiver function, and an actuator operated by a signal sent from the receiving device, and in which power with which the node apparatus operates is supplied from the power generating device, and the power generated in the power generating device is increased and decreased by the actuator.Type: ApplicationFiled: September 28, 2018Publication date: April 4, 2019Inventors: Sadashi SHIMODA, Yusuke TAKEUCHI, Taro YAMASAKI
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Patent number: 9875154Abstract: Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.Type: GrantFiled: July 1, 2015Date of Patent: January 23, 2018Assignee: SII SEMICONDUCTOR CORPORATIONInventors: Masanori Miyagi, Taro Yamasaki
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Publication number: 20170017543Abstract: Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.Type: ApplicationFiled: July 1, 2015Publication date: January 19, 2017Inventors: Masanori MIYAGI, Taro YAMASAKI
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Patent number: 9548530Abstract: [Problem to be Solved] To provide an antenna which can be used in a wide band. [Solution] An antenna 10A includes a dielectric substrate 11, an unbalanced power supply member 12 having a non-power supply unit 23 and a power supply unit 24, a resonance conductor 13 having a connection area 26, a first resonance area 27 and a second resonance area 28, a grounding conductor 14 having a first ground area 32 and a second ground area 33, and a radiation conductor 15 having a first radiation area 37 and a second radiation area 38. At the antenna 10A, first to third radiation stepped portions 42a to 42c are formed at a first rear end portion 41 of the second radiation area 38, and first to third radiation stepped portions 44a to 44c are formed at a second rear end portion 43 of the second radiation area 38.Type: GrantFiled: January 23, 2014Date of Patent: January 17, 2017Assignees: NOISE LABORATORY CO., LTD., TOYOTA MOTOR CORPORATIONInventors: Takayuki Kubo, Takeshi Ishida, Toru Uno, Taro Yamasaki, Hisashi Morishita, Masao Sakuma, Akihiko Nojima, Hiroki Keino, Keigo Yuba
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Publication number: 20150357706Abstract: [Problem to be Solved] To provide an antenna which can be used in a wide band. [Solution] An antenna 10A includes a dielectric substrate 11, an unbalanced power supply member 12 having a non-power supply unit 23 and a power supply unit 24, a resonance conductor 13 having a connection area 26, a first resonance area 27 and a second resonance area 28, a grounding conductor 14 having a first ground area 32 and a second ground area 33, and a radiation conductor 15 having a first radiation area 37 and a second radiation area 38. At the antenna 10A, first to third radiation stepped portions 42a to 42c are formed at a first rear end portion 41 of the second radiation area 38, and first to third radiation stepped portions 44a to 44c are formed at a second rear end portion 43 of the second radiation area 38.Type: ApplicationFiled: January 23, 2014Publication date: December 10, 2015Inventors: Takayuki KUBO, Takeshi ISHIDA, Toru UNO, Taro YAMASAKI, Hisashi MORISHITA, Masao SAKUMA, Akihiko NOJIMA, Hiroki KEINO, Keigo YUBA
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Publication number: 20150301889Abstract: Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Inventors: Masanori MIYAGI, Taro YAMASAKI
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Patent number: 8791686Abstract: The voltage reference circuit includes: a first MOS transistor; a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor and having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value and a K value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current; and a fourth MOS transistor having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current.Type: GrantFiled: September 11, 2012Date of Patent: July 29, 2014Assignee: Seiko Instruments Inc.Inventors: Taro Yamasaki, Fumiyasu Utsunomiya
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Patent number: 8748790Abstract: Provided is a proximity sensor using a photosensor, which is easy to use and reduced in power consumption. In the proximity sensor, a first photosensor is used to detect a change in amount of ambient light entering the first photosensor, which is caused when a finger is coming close thereto, and a detection signal is output based on a result of the detection. The photosensor includes, for example, one or a plurality of PN junction elements connected in parallel.Type: GrantFiled: March 23, 2011Date of Patent: June 10, 2014Assignee: Seiko Instruments Inc.Inventors: Fumiyasu Utsunomiya, Taro Yamasaki, Isamu Fujii
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Patent number: 8730753Abstract: A nonvolatile semiconductor memory device, having a booster circuit capable of performing a boost operation with appropriate boost voltage arrival time without increasing the circuit size. The nonvolatile semiconductor memory device includes a timing generator circuit and a current load circuit which applies a current load to an output of a booster unit according to a signal from the timing generator circuit, thereby achieving an appropriate boost voltage arrival time by using the current load circuit in concert with the operation of erasing or writing on memory cells.Type: GrantFiled: February 26, 2013Date of Patent: May 20, 2014Assignee: Seiko Instruments Inc.Inventor: Taro Yamasaki
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Patent number: 8536673Abstract: Provided is a light receiving circuit for detecting a change in amount of light, in which an input circuit at a subsequent stage is compact and inexpensive and current consumption is low. The light receiving circuit includes: a photoelectric conversion element for supplying a current corresponding to an amount of incident light; an N-channel MOS transistor including a drain supplied with the current from the photoelectric conversion element; and a control circuit for controlling a gate voltage of the NMOS transistor via a low pass filter so that a drain voltage of the N-channel MOS transistor becomes a desired voltage.Type: GrantFiled: April 22, 2011Date of Patent: September 17, 2013Assignee: Seiko Instruments Inc.Inventors: Fumiyasu Utsunomiya, Taro Yamasaki, Isamu Fujii
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Publication number: 20130229881Abstract: A nonvolatile semiconductor memory device, having a booster circuit capable of performing a boost operation with appropriate boost voltage arrival time without increasing the circuit size. The nonvolatile semiconductor memory device includes a timing generator circuit and a current load circuit which applies a current load to an output of a booster unit according to a signal from the timing generator circuit, thereby achieving an appropriate boost voltage arrival time by using the current load circuit in concert with the operation of erasing or writing on memory cells.Type: ApplicationFiled: February 26, 2013Publication date: September 5, 2013Applicant: SEIKO INSTRUMENTS INC.Inventor: Taro YAMASAKI
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Publication number: 20130076331Abstract: The voltage reference circuit includes: a first MOS transistor; a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor and having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value and a K value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current; and a fourth MOS transistor having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current.Type: ApplicationFiled: September 11, 2012Publication date: March 28, 2013Applicant: SEIKO INSTRUMENTS INC.Inventors: Taro YAMASAKI, Fumiyasu UTSUNOMIYA
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Publication number: 20110272749Abstract: Provided is a light receiving circuit for detecting a change in amount of light, in which an input circuit at a subsequent stage is compact and inexpensive and current consumption is low. The light receiving circuit includes: a photoelectric conversion element for supplying a current corresponding to an amount of incident light; an N-channel MOS transistor including a drain supplied with the current from the photoelectric conversion element; and a control circuit for controlling a gate voltage of the NMOS transistor via a low pass filter so that a drain voltage of the N-channel MOS transistor becomes a desired voltage.Type: ApplicationFiled: April 22, 2011Publication date: November 10, 2011Inventors: Fumiyasu UTSUNOMIYA, Taro YAMASAKI, Isamu FUJII
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Publication number: 20110234302Abstract: Provided is a proximity sensor using a photosensor, which is easy to use and reduced in power consumption. In the proximity sensor, a first photosensor is used to detect a change in amount of ambient light entering the first photosensor, which is caused when a finger is coming close thereto, and a detection signal is output based on a result of the detection. The photosensor includes, for example, one or a plurality of PN junction elements connected in parallel.Type: ApplicationFiled: March 23, 2011Publication date: September 29, 2011Inventors: Fumiyasu UTSUNOMIYA, Taro YAMASAKI, Isamu FUJII
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Publication number: 20110109364Abstract: Provided is an input circuit having hysteresis characteristics that is capable of operating in a wide range of power supply voltage conditions while suppressing power supply voltage dependence of a hysteresis voltage and a response speed. The input circuit is provided with: a circuit for obtaining a small hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 to 103) and an inverter (501)); and a circuit for obtaining a large hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 and 104) and the inverter (501)).Type: ApplicationFiled: November 10, 2010Publication date: May 12, 2011Inventors: Taro Yamasaki, Fumiyasu Utsunomiya
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Patent number: 4690553Abstract: Road surface condition detection system comprising light projector means for projecting light including the infrared region of the spectrum to a road surface to sense the condition thereof, the infrared having wavelengths at which the reflectance of snow is smaller than that of the road surface in a dry condition, light receiving means for receiving light reflected from the road surface, comparisons means for comparing the output signals generated from the light receiving means with reference signal levels corresponding to dry, wet, snowy and frozen conditions, and judging means for judging the road surface to be one of the conditions in accordance with results of comparison.Type: GrantFiled: June 12, 1980Date of Patent: September 1, 1987Assignee: Omron Tateisi Electronics Co.Inventors: Hiroshi Fukamizu, Masaji Nakano, Kunio Iba, Taro Yamasaki, Kenji Sano