Patents by Inventor Taro Yoshino

Taro Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200285118
    Abstract: To shorten the response time during falling time of making a transition from a state in which a horizontal field passes through a liquid crystal layer to a state in which the horizontal field does not pass through the liquid crystal layer without necessitating a complicated structure of an electrode for generating the horizontal field. A first alignment film has a main surface having an alignment capability of aligning liquid crystal molecules in a particular alignment direction. A partition is arranged on at least a first field concentrated part at a first pixel electrode, and a second field concentrated part at the second pixel electrode. A surface of a second alignment film covering the partition has an alignment capability of aligning the liquid crystal molecules in the particular alignment direction. The partition partitions the liquid crystal layer in a direction parallel to an extension direction of the liquid crystal layer.
    Type: Application
    Filed: April 19, 2018
    Publication date: September 10, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Taro YOSHINO, Toshiaki FUJINO
  • Patent number: 7612378
    Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: November 3, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiko Toyoda, Naoki Nakagawa, Taro Yoshino
  • Publication number: 20060214229
    Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.
    Type: Application
    Filed: March 16, 2006
    Publication date: September 28, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yoshihiko Toyoda, Naoki Nakagawa, Taro Yoshino