Patents by Inventor Tarou Fukunaga

Tarou Fukunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7698667
    Abstract: To provide a pattern correction apparatus which enables easy correction of a trace which is not present on trace grids, a pattern correction apparatus which makes a correction to a pattern of an integrated circuit includes a trace movement section for moving, among traces forming the pattern of the integrated circuit, a trace which is not present on trace grids to a position above the trace grids; a pattern correction section for making a correction to the pattern; and a trace pitch optimization section for optimizing a trace pitch between traces forming a pattern corrected by the pattern correction section.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Mitsukiyo Matsui, Tarou Fukunaga, Mie Yamanaka, Hiroki Tomoshige, Maya Ishino, Muneaki Kyoya, Satoru Nishioka
  • Publication number: 20080028344
    Abstract: To provide a pattern correction apparatus which enables easy correction of a trace which is not present on trace grids, a pattern correction apparatus which makes a correction to a pattern of an integrated circuit includes a trace movement section for moving, among traces forming the pattern of the integrated circuit, a trace which is not present on trace grids to a position above the trace grids; a pattern correction section for making a correction to the pattern; and a trace pitch optimization section for optimizing a trace pitch between traces forming a pattern corrected by the pattern correction section.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 31, 2008
    Inventors: Mitsukiyo Matsui, Tarou Fukunaga, Mie Yamanaka, Hiroki Tomoshige, Maya Ishino, Muneaki Kyoya, Satoru Nishioka
  • Publication number: 20060129964
    Abstract: A placement 103 of a macrocell is applied to a net list 102 formed by the logic synthesis by using the automatic layout tool, physical information of the macrocell is extracted in a physical information extracting step 104, and a net list 106 including the physical information is generated by attaching the extracted physical information to the instance name of the macrocell. Since the physical information such as placement coordinate, utilization factor, voltage drop value, and the like are attached to the instance name of the macrocell, the physical information can be grasped without reference to the layout data, and also analysis of the simulation and correction of the layout data can be facilitated. Also, since the placement position designation constraint is generated from the net list including the physical information, the high-quality layout design can be carried out.
    Type: Application
    Filed: December 9, 2005
    Publication date: June 15, 2006
    Inventors: Harumi Shibasaki, Tarou Fukunaga, Maya Ishino, Kouhei Nakai