Patents by Inventor Tarpan Dixit
Tarpan Dixit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230316593Abstract: A method includes receiving data indicating a plurality of dimensions of a manufactured device. The method further includes providing the data to a trained machine learning model. The method further includes receiving, from the trained machine learning model, a synthetic microscopy image associated with the manufactured device, wherein the synthetic microscopy image is generated in view of the first data. The method further includes performing at least one of (i) outputting the synthetic microscopy image to a display or (ii) performing one or more operations on the synthetic microscopy image.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Abhinav Kumar, Adrienne Melissa Martin Bergh, Tarpan Dixit
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Patent number: 11416977Abstract: Methods, systems, and non-transitory computer readable medium are described for automated image measurement for process development and optimization. An example method may include receiving an image of a product associated with a manufacturing process, wherein the product comprises a plurality of structures; identifying, using a trained machine learning model, a segment of the image that comprises a structure of the plurality of structures; determining a plurality of image measurements of the segment that comprises the structure; and storing the plurality of image measurements.Type: GrantFiled: March 10, 2020Date of Patent: August 16, 2022Assignee: Applied Materials, Inc.Inventors: Abhinav Kumar, Tarpan Dixit
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Publication number: 20210287354Abstract: Methods, systems, and non-transitory computer readable medium are described for automated image measurement for process development and optimization. An example method may include receiving an image of a product associated with a manufacturing process, wherein the product comprises a plurality of structures; identifying, using a trained machine learning model, a segment of the image that comprises a structure of the plurality of structures; determining a plurality of image measurements of the segment that comprises the structure; and storing the plurality of image measurements.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Inventors: Abhinav Kumar, Tarpan Dixit
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Patent number: 8110828Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.Type: GrantFiled: June 9, 2011Date of Patent: February 7, 2012Assignee: Solyndra LLCInventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
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Publication number: 20110259391Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.Type: ApplicationFiled: June 9, 2011Publication date: October 27, 2011Inventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
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Patent number: 7964418Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.Type: GrantFiled: August 16, 2007Date of Patent: June 21, 2011Assignee: Solyndra LLCInventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
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Patent number: 7398693Abstract: The present invention generally relates to methods for the rapid thermal processing (RTP) of a substrate. Embodiments of the invention include controlling a thermal process using either a real-time adaptive control algorithm or by using a control algorithm that is selected from a suite of fixed control algorithms designed for a variety of substrate types. Selection of the control algorithm is based on optical properties of the substrate measured during the thermal process. In one embodiment, a combination of control algorithms are used, wherein the majority of lamp groupings are controlled with a fixed control algorithm and a substantially smaller number of lamp zones are controlled by an adaptive control algorithm.Type: GrantFiled: March 30, 2006Date of Patent: July 15, 2008Assignee: Applied Materials, Inc.Inventors: Joseph Michael Ranish, Tarpan Dixit, Dean Jennings, Balasubramanian Ramachandran, Aaron Hunter, Wolfgang Aderhold, Bruce Adams, Wen Teh Chang
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Publication number: 20080041439Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.Type: ApplicationFiled: August 16, 2007Publication date: February 21, 2008Inventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
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Publication number: 20070238202Abstract: The present invention generally relates to methods for the rapid thermal processing (RTP) of a substrate. Embodiments of the invention include controlling a thermal process using either a real-time adaptive control algorithm or by using a control algorithm that is selected from a suite of fixed control algorithms designed for a variety of substrate types. Selection of the control algorithm is based on optical properties of the substrate measured during the thermal process. In one embodiment, a combination of control algorithms are used, wherein the majority of lamp groupings are controlled with a fixed control algorithm and a substantially smaller number of lamp zones are controlled by an adaptive control algorithm.Type: ApplicationFiled: March 30, 2006Publication date: October 11, 2007Inventors: Joseph Ranish, Tarpan Dixit, Dean Jennings, Balasubramanian Ramachandran, Aaron Hunter, Wolfgang Aderhold, Bruce Adams, Wen Chang
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Patent number: 7112763Abstract: A rapid thermal processing (RTP) system including a transmission pyrometer monitoring the temperature dependent absorption of the silicon wafer for radiation from the RTP lamps at a reduced power level. A look-up table is created relating unnormalized values of photodetector photocurrents with wafer and radiant lamp temperatures. A calibrating step measures the photocurrent with known wafer and lamp temperatures and all photocurrents measured thereafter are accordingly normalized. The transmission pyrometer may be used for closed loop control for thermal treatments below 500° C. or used in the pre-heating phase for a higher temperature process including radiation pyrometry in closed loop control. The pre-heating temperature ramp rate may be controlled by measuring the initial ramp rate and readjusting the lamp power accordingly. Radiation and transmission pyrometers may be included in an integrated structure with a beam splitter dividing radiation from the wafer.Type: GrantFiled: October 26, 2004Date of Patent: September 26, 2006Assignee: Applied Materials, Inc.Inventors: Aaron Hunter, Rajesh S. Ramanujam, Balasubramanian Ramachandran, Corina Elena Tanasa, Tarpan Dixit
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Publication number: 20060086713Abstract: A rapid thermal processing (RTP) system including a transmission pyrometer monitoring the temperature dependent absorption of the silicon wafer for radiation from the RTP lamps at a reduced power level. A look-up table is created relating unnormalized values of photodetector photocurrents with wafer and radiant lamp temperatures. A calibrating step measures the photocurrent with known wafer and lamp temperatures and all photocurrents measured thereafter are accordingly normalized. The transmission pyrometer may be used for closed loop control for thermal treatments below 500° C. or used in the pre-heating phase for a higher temperature process including radiation pyrometry in closed loop control. The pre-heating temperature ramp rate may be controlled by measuring the initial ramp rate and readjusting the lamp power accordingly. Radiation and transmission pyrometers may be included in an integrated structure with a beam splitter dividing radiation from the wafer.Type: ApplicationFiled: October 26, 2004Publication date: April 27, 2006Inventors: Aaron Hunter, Rajesh Ramanujam, Balasubramanian Ramachandran, Cornia Tanasa, Tarpan Dixit