Abstract: The present invention addresses the need for improved virtualized cloud infrastructure policy implementation and management in order allow real-time monitoring and optimization of virtualized resources. It provides systems and methods for real-time cloud infrastructure policy implementation and management that include a plurality of host devices, a plurality of real-time probe agents associated with the plurality of host devices operating on each of the plurality of host devices, and a policy engine communicatively coupled to the plurality of host devices and containing a policy associated with an application program deployed in at least one of the plurality of host devices. The policy engine is programmed to monitor in real time changes in deployment of the application program across the plurality of host devices and to push the policy to the real-time probe agent operating on each host device on which the application program is deployed.

Abstract: The system may be configured to perform operations including receiving a transaction history comprising transaction information associated with a plurality of transactions for an entity; analyzing transaction information associated with a transaction of the plurality of transactions; and detecting a leakage event associated with the transaction. Detecting the leakage event may comprise determining a payment method for the transaction in response to the analyzing the transaction information; and comparing the payment method to a desired payment method, wherein the leakage event is detected in response to the payment method differing from the desired payment method.

Abstract: The present invention addresses the need for improved virtualized cloud infrastructure policy implementation and management in order allow real-time monitoring and optimization of virtualized resources. It provides systems and methods for real-time cloud infrastructure policy implementation and management that include a plurality of host devices, a plurality of real-time probe agents associated with the plurality of host devices operating on each of the plurality of host devices, and a policy engine communicatively coupled to the plurality of host devices and containing a policy associated with an application program deployed in at least one of the plurality of host devices. The policy engine is programmed to monitor in real time changes in deployment of the application program across the plurality of host devices and to push the policy to the real-time probe agent operating on each host device on which the application program is deployed.

Abstract: Disclosed are methods and topical compositions for applying bacteria to skin, scalp and hair. The topical compositions include bacteria in a suitable base vehicle comprising honey for applying the bacteria to skin, scalp and hair. The base vehicle may include additional components such as, but not limited to, plant-based products, micro-nutrients, emollients and plant-sourced emulsifiers, and anti-oxidants, among other components. The topical compositions may be utilized in methods for treating and/or preventing skin, scalp, and hair conditions such as, but not limited to, dry skin, dry scalp, dandruff, psoriasis, cradle cap, seborrheic dermatitis, and/or eczema.

Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

Abstract: Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.

Abstract: Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.

Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

Abstract: Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.

Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.

Abstract: Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor.

Abstract: Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.

Abstract: Provided is a digital-to-analog converter configured to mitigate data dependent jitter of switch driver signals. The digital-to-analog converter is configured to produce data patterns of “0001000”. The digital-to-analog converter includes a digital portion that includes a digital data input component, an analog portion, and a conversion component. The conversion component includes a decoder configured to split a first data stream comprising a set of digital data into a first data sub-stream and a second data sub-stream, and a second data stream comprising another set of digital data into a third data sub-stream and a fourth data sub-stream. The conversion component also includes a first pair of drivers, a second pair of drivers, a third pair of drivers, and a fourth pair of drivers, wherein respective drivers of the first, second, third, and fourth pairs of drivers are configured to output respective data patterns comprising at least three consecutive identical bits.

Abstract: A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to selectively connecting the first node, a first analog signal is supplied to the latch first input. Subsequent to resetting the latch, the first analog signal is captured and the latch output supplies a digital signal responsive to the captured first analog signal.

Abstract: A linear source follower amplifier is provided with a first metal-oxide semiconductor (MOS) field effect transistor (FET) having a gate to accept an ac input signal and a source to supply an ac output signal. A second MOS FET has a gate to accept the ac input signal, a source connected to the drain of the first MOS FET. A third MOS FET has a drain connected to the source of the first MOS FET, a gate connected to the drain of the second MOS FET, and a source connected to a first reference voltage. A fourth MOS FET has a drain and a gate connected to the drain of the second MOS FET and a source connected to the first reference voltage. A current source has an input connected to a second reference voltage, and an output connected to the drain of the first MOS FET.

Abstract: A full-duplex wire-line transceiver is provided with echo cancellation line driver. The transceiver has an impedance matching network with a network interface, and a transmit interface to accept a differential transmit signal for transmission via the network. The impedance matching network has a receive interface to supply a differential receive signal accepted at the network interface, where the transmit interface is coupled to the receive interface. A hybrid circuit has an input to accept the differential receive signal combined with a coupled differential transmit signal, and input to accept a differential echo cancellation (EC) signal. The hybrid circuit has an output to supply the differential receive signal with the coupled differential transmit signal attenuated in response to the differential EC signal. A line driver uses an active current mirror to generate matched transmit and EC signals.