Patents by Inventor Taryn J. Davis

Taryn J. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10553503
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 10504807
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Patent number: 10217682
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Publication number: 20180350702
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Patent number: 10134649
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 10068812
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20180226308
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Application
    Filed: April 10, 2018
    Publication date: August 9, 2018
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Patent number: 10032683
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Patent number: 10008427
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 9911716
    Abstract: A lidded or lidless flip-chip package includes two or more polygon shaped dies. The polygon dies may be interconnected to a substrate or to an interposer interconnected to a substrate. The interposer may be similarly shaped with respect to the polygon die(s). For the lidless or lidded package, the package may include underfill under the polygon dies surrounding associated interconnects. For the lidded package, the package may also include thermal interface materials, seal bands, and a lid. The polygon die package reduces shear stress between the polygon die/interposer and associated underfill as compared to square or rectangular shaped die/interposer of the same area. The polygon dies further maximize the utilization of a wafer from upon which the polygon dies are fabricated. The multi polygon die package may allow for a significant reduction of the polygon die to polygon die relative to the spacing and may reduce signal interconnect time.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Taryn J. Davis, Tuhin Sinha
  • Publication number: 20180047644
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 15, 2018
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20180019172
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 18, 2018
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 9818655
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20170271219
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20170194221
    Abstract: A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 6, 2017
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20170162455
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 8, 2017
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Publication number: 20160372391
    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 22, 2016
    Inventors: Taryn J. Davis, Jonathan R. Fry, Terence L. Kane, Christopher F. Klabes, Andrew J. Martin, Vincent J. McGahay, Kathryn E. Schlichting, Melissa A. Smith
  • Patent number: 9437515
    Abstract: Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Taryn J. Davis, Chenzhou Lian, Yi Pan, Kamal K. Sikka, Jeffrey A. Zitz
  • Publication number: 20160225742
    Abstract: A lidded or lidless flip-chip package includes two or more polygon shaped dies. The polygon dies may be interconnected to a substrate or to an interposer interconnected to a substrate. The interposer may be similarly shaped with respect to the polygon die(s). For the lidless or lidded package, the package may include underfill under the polygon dies surrounding associated interconnects. For the lidded package, the package may also include thermal interface materials, seal bands, and a lid. The polygon die package reduces shear stress between the polygon die/interposer and associated underfill as compared to square or rectangular shaped die/interposer of the same area. The polygon dies further maximize the utilization of a wafer from upon which the polygon dies are fabricated. The multi polygon die package may allow for a significant reduction of the polygon die to polygon die relative to the spacing and may reduce signal interconnect time.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Taryn J. Davis, Tuhin Sinha
  • Patent number: 9401315
    Abstract: A semiconductor device package which includes a semiconductor package, a semiconductor device joined to the semiconductor package; and a lid to be placed over the semiconductor device and joined to the semiconductor package. The lid includes: a block of a first material having a first surface and a second surface, the second surface facing the semiconductor device, the block having perforations extending between the first surface and the second surface; inserts for filling the perforations, each of the inserts being made of a second material, at least one of the inserts protrudes beyond the second surface towards the semiconductor device; and a bonding material to bond the inserts to the block so that the at least one of the inserts protrudes beyond the second surface towards the semiconductor device. Also included is a method of assembling a semiconductor device package.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: July 26, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Paul F. Bodenweber, Taryn J. Davis, Marcus E. Interrante, Chenzhou Lian, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Hilton T. Toy