Patents by Inventor Tasao Soga

Tasao Soga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8907475
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20130286621
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: June 21, 2013
    Publication date: October 31, 2013
    Inventors: Hanae SHIMOKAWA, Tasao SOGA, Hiroaki OKUDAIRA, Toshiharu ISHIDA, Tetsuya NAKATSUKA, Yoshiharu INABA, Asao NISHIMURA
  • Patent number: 8503189
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: August 6, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 8125090
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: February 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Patent number: 8022551
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Patent number: 8004075
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: August 23, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Publication number: 20100289148
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Inventors: Tasao SOGA, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Publication number: 20100214753
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: May 4, 2010
    Publication date: August 26, 2010
    Inventors: Hanae SHIMOKAWA, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 7722962
    Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tasao Soga, Hanae Hata, Toshiharu Ishida, Kanko Ishida, legal representative, Tetsuya Nakatsuka, Masahide Okamoto, Kazuma Miura
  • Patent number: 7709746
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 4, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 7671465
    Abstract: A power semiconductor module having an increased reliability against thermal fatigue includes a power semiconductor element, a lower-side electrode connected to the lower side of the element, a first insulating substrate connected to the upper side of the lower-side electrode and having metallic foils bonded on both surfaces thereof, an upper-side electrode connected to the upper side of the power semiconductor element, a second insulating substrate connected to the upper side of the upper-side electrode and having metallic foils bonded on both surfaces thereof, a first heat spreader connected to the lower side of the first insulating substrate, and a second heat spreader connected to the upper side of the second insulating substrate. The power semiconductor element and the first and second insulating substrates are sealed with a resin.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: March 2, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Sunao Funakoshi, Katsumi Ishikawa, Tasao Soga
  • Patent number: 7547966
    Abstract: A power semiconductor module with its thermal resistance and overall size reduced. Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering. Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing. Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders. The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 16, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Sunao Funakoshi, Katsumi Ishikawa, Tasao Soga
  • Publication number: 20090116197
    Abstract: A power semiconductor module includes first and second insulating substrates, a power semiconductor device joined directly or through another element to opposite sides of the first and second insulating substrates and first and second heat spreaders joined with joining material having fluidity upon joining so as to put the first and second insulating substrates between the first and second heat spreaders. When the power semiconductor module is fabricated, the first and second insulating substrates are joined to the first and second heat spreaders, respectively, in the state that weight bearing on joining material is reduced by means of resilient member.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 7, 2009
    Inventors: Sunao FUNAKOSHI, Katsumi Ishikawa, Tasao Soga
  • Publication number: 20080224303
    Abstract: A power semiconductor module with its thermal resistance and overall size reduced. Insulating substrates with electrode metal layers disposed thereon are joined to both the surfaces of a power semiconductor chip by using, for example, soldering. Metal layers are disposed also on the reverse surfaces of the insulating substrates and the metal layers are joined to the heat spreaders by using brazing. Heat radiating fins are provided on the heat radiating surface of at least one of the heat spreaders. The heat radiating side of each of the heat spreaders is covered by a casing to form a refrigerant chamber through which refrigerant flows to remove heat transmitted from the semiconductor chip to the heat spreader.
    Type: Application
    Filed: October 17, 2007
    Publication date: September 18, 2008
    Inventors: Sunao Funakoshi, Katsumi Ishikawa, Tasao Soga
  • Publication number: 20070246833
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Application
    Filed: April 24, 2007
    Publication date: October 25, 2007
    Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Publication number: 20070216013
    Abstract: A power semiconductor module having an increased reliability against thermal fatigue includes a power semiconductor element, a lower-side electrode connected to the lower side of the element, a first insulating substrate connected to the upper side of the lower-side electrode and having metallic foils bonded on both surfaces thereof, an upper-side electrode connected to the upper side of the power semiconductor element, a second insulating substrate connected to the upper side of the upper-side electrode and having metallic foils bonded on both surfaces thereof, a first heat spreader connected to the lower side of the first insulating substrate, and a second heat spreader connected to the upper side of the second insulating substrate. The power semiconductor element and the first and second insulating substrates are sealed with a resin.
    Type: Application
    Filed: January 25, 2007
    Publication date: September 20, 2007
    Inventors: Sunao Funakoshi, Katsumi Ishikawa, Tasao Soga
  • Patent number: 7259465
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: August 21, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Publication number: 20070031279
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Application
    Filed: April 7, 2006
    Publication date: February 8, 2007
    Applicant: Renesas Technology Corporation
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Patent number: 7145236
    Abstract: A semiconductor module solder bonding of high reliability in which the heat resisting properties of the circuit substrate and electronic parts are taken into consideration. In order to achieve this, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: December 5, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kazuma Miura, Hanae Shimokawa, Koji Serizawa, Tasao Soga, Tetsuya Nakatsuka
  • Patent number: 7075183
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu etc. and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: July 11, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh