Patents by Inventor Tassa Yang

Tassa Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory circuit and method of programming memory circuit
    Patent number: 9627060
    Abstract: A method includes applying a first voltage setting to a memory cell for a first period of time in response to a command for programming a first logical state to the memory cell, obtaining a first stored logical state of the memory cell after the applying the first voltage setting operation, and if the first stored logical state differs from the first logical state, applying a second voltage setting to the memory cell.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chieh Chiu, Chih-Yang Chang, Tassa Yang, Wen-Ting Chu
  • MEMORY CIRCUIT AND METHOD OF PROGRAMMING MEMORY CIRCUIT
    Publication number: 20160111156
    Abstract: A method includes applying a first voltage setting to a memory cell for a first period of time in response to a command for programming a first logical state to the memory cell, obtaining a first stored logical state of the memory cell after the applying the first voltage setting operation, and if the first stored logical state differs from the first logical state, applying a second voltage setting to the memory cell.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Yi-Chieh CHIU, Chih-Yang CHANG, Tassa YANG, Wen-Ting CHU
  • Memory circuit and method of programming memory circuit
    Patent number: 9224470
    Abstract: A method includes applying a first voltage setting to a first node and a second node of a selected memory cell for a first predetermined period of time in response to a command for programming a first logical state to the selected memory cell. A first stored logical state of the selected memory cell is obtained after the applying the first voltage setting operation. If the first stored logical state differs from the first logical state, a second voltage setting is applied to the first node and the second node of the selected memory cell; and a first retrial is performed. The first retrial includes applying the first voltage setting to the first node and the second node of the selected memory cell for the first predetermined period of time.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: December 29, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chieh Chiu, Chih-Yang Chang, Tassa Yang, Wen-Ting Chu