Abstract: Embodiments of the invention are directed to a method and resulting structures for identifying an integrated circuit (IC) chip using optically-unique features. In a non-limiting embodiment of the invention, an imaging device generates an image of the chip. One or more optical features of the chip within the image can be determined and stored in a local or remote database. Metadata associated with the chip can be generated and linked with the one or more optical features of the chip and a unique identifier of the chip in the database.

Abstract: Embodiments of the invention are directed to a method and resulting structures for identifying an integrated circuit (IC) chip using optically-unique features. In a non-limiting embodiment of the invention, an imaging device generates an image of the chip. One or more optical features of the chip within the image can be determined and stored in a local or remote database. Metadata associated with the chip can be generated and linked with the one or more optical features of the chip and a unique identifier of the chip in the database.

Abstract: A semiconductor comprising a front end of line portion including a logical processing unit (LPU) and a second LPU. The first LPU configured to perform a first operation and the second LPU configured to perform a second operation following the first operation. A back end of line portion including a plurality of wiring levels, and further including a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels. The power gate and clock gate are further electrically connected to the first LPU by an enable wire. The power gate and clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU. A signal wire is electrically connected to the first LPU and to the latch.