Abstract: An interface device is provided between a test head and a device under test (DUT). A socket board includes sockets each configured to mount a DUT, and a socket PCB having a first face that mounts the sockets and a second face provided with multiple back face electrodes. An interposer has a first face provided with multiple deformable electrodes and a second face provided with multiple non-deformable electrodes and is configured such that the multiple deformable electrodes are in contact with the multiple back face electrodes of the socket PCB. An FPC cable has multiple electrode pads to be coupled with the multiple non-deformable electrodes on the second face of the first interposer.

Abstract: An interface device is provided between a test head and a DUT. In the interface device, each pin electronics IC is coupled to a DUT via an FPC cable.

Abstract: An interface apparatus is provided between a test head and a DUT. The interface apparatus includes a frontend module configured of multiple pin electronics ICs in the form of a module.

Abstract: An interface device is provided between a test head and a DUT. The interface device includes pin electronics ICs, RAM, a pin controller, and nonvolatile memory. The RAM stores data based on a device signal received from the DUT by means of the multiple pin electronics ICs. The pin controller controls the multiple pin electronics ICs according to a control signal from the test head. The multiple pin electronics ICs, the RAM, and the pin controller are mounted on a pin electronics PCB.

Abstract: A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state.

Abstract: A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween.

Abstract: A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween.

Abstract: A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state.

Abstract: A detection apparatus is provided. The detection apparatus includes; a multi-strobe generating section that generates a plurality of strobe signals with phases different from one another; a plurality of acquiring sections each of which acquires a signal value of a signal under measurement at a timing of each of the plurality of strobe signals; a plurality of changing point detecting sections that detect a fact that there is a changing point of the signal under measurement between two adjacent strobe signals when two signal values which are acquired in accordance with the two adjacent strobe signals are different from one another; a mask setting section that sets the changing point detecting section to be enabled among the plurality of changing point detecting sections; and a changing timing output section that outputs a changing timing of the signal under measurement based on an output of the enabled changing point detecting section.

Abstract: There is provided a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto. The test apparatus includes a pattern generating section that generates writing data to be written into the memory under test, a first address generating section having an address information storing section that stores thereon address information indicating an address of the memory under test to which the writing data is to be written, and a waveform shaping section that generates an address signal by outputting one or more pulses at a predetermined time interval during a time period determined in accordance with the address information stored on the address information storing section.

Abstract: There is provided a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto. The test apparatus includes a pattern generating section that generates writing data to be written into the memory under test, a first address generating section having an address information storing section that stores thereon address information indicating an address of the memory under test to which the writing data is to be written, and a waveform shaping section that generates an address signal by outputting one or more pulses at a predetermined time interval during a time period determined in accordance with the address information stored on the address information storing section.

Abstract: A detection apparatus is provided. The detection apparatus includes; a multi-strobe generating section that generates a plurality of strobe signals with phases different from one another; a plurality of acquiring sections each of which acquires a signal value of a signal under measurement at a timing of each of the plurality of strobe signals; a plurality of changing point detecting sections that detect a fact that there is a changing point of the signal under measurement between two adjacent strobe signals when two signal values which are acquired in accordance with the two adjacent strobe signals are different from one another; a mask setting section that sets the changing point detecting section to be enabled among the plurality of changing point detecting sections; and a changing timing output section that outputs a changing timing of the signal under measurement based on an output of the enabled changing point detecting section.