Patents by Inventor Tasuku TAKEUCHI

Tasuku TAKEUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945886
    Abstract: A cured resin formation method including an applying step of applying an ultraviolet curable resin on a base; and a curing step of curing the ultraviolet curable resin by irradiating the ultraviolet curable resin applied in the applying step with ultraviolet rays, in which in the curing step, the ultraviolet curable resin is irradiated with ultraviolet rays while cooling the ultraviolet curable resin, so that a difference between an ordinary temperature of the ultraviolet curable resin and a temperature of the ultraviolet curable resin when irradiated with ultraviolet rays is within a set temperature difference set in advance.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 2, 2024
    Assignee: FUJI CORPORATION
    Inventors: Tasuku Takeuchi, Ryojiro Tominaga
  • Publication number: 20220298267
    Abstract: A cured resin formation method including an applying step of applying an ultraviolet curable resin on a base; and a curing step of curing the ultraviolet curable resin by irradiating the ultraviolet curable resin applied in the applying step with ultraviolet rays, in which in the curing step, the ultraviolet curable resin is irradiated with ultraviolet rays while cooling the ultraviolet curable resin, so that a difference between an ordinary temperature of the ultraviolet curable resin and a temperature of the ultraviolet curable resin when irradiated with ultraviolet rays is within a set temperature difference set in advance.
    Type: Application
    Filed: July 31, 2019
    Publication date: September 22, 2022
    Applicant: FUJI CORPORATION
    Inventors: Tasuku TAKEUCHI, Ryojiro TOMINAGA
  • Publication number: 20220279658
    Abstract: In a case where a circuit wiring is formed on a resin member by three-dimensional additive manufacturing, a method for manufacturing the circuit wiring by three-dimensional additive manufacturing capable of suppressing swelling or cracking of the circuit wiring is provided. A method for manufacturing a circuit wiring by three-dimensional additive manufacturing includes a discharging step of discharging a fluid containing a metal particle onto a resin member formed of a resin material; and a circuit wiring forming step of forming a circuit wiring by heating the fluid containing the metal particle discharged onto the resin member at a heating temperature to be cured, and the heating being performed at the heating temperature based on a glass transition point of the resin material, a linear expansion coefficient of the resin material, and a room temperature.
    Type: Application
    Filed: July 31, 2019
    Publication date: September 1, 2022
    Applicant: FUJI CORPORATION
    Inventors: Ryojiro TOMINAGA, Ryo SAKAKIBARA, Tasuku TAKEUCHI, Yoshitaka HASHIMOTO, Kenji TSUKADA
  • Publication number: 20220279657
    Abstract: To provide an electronic circuit production method using 3D layer shaping capable of producing an electronic circuit having improved electrical properties and mechanical properties by utilizing characteristics of a fluid containing a metal particle by selectively using the fluid containing the metal particle. The electronic circuit production method using 3D layer shaping, the method including a wiring forming step of forming a wiring by applying a fluid containing a nano-sized metal nanoparticle on an insulating member and curing the applied fluid containing the metal nanoparticle; and a connection terminal forming step of forming a connection terminal electrically connected to the wiring by applying a fluid containing a micro-sized metal microparticle and curing the applied fluid containing the metal microparticle.
    Type: Application
    Filed: July 30, 2019
    Publication date: September 1, 2022
    Applicant: FUJI CORPORATION
    Inventors: Ryojiro TOMINAGA, Kenji TSUKADA, Ryo SAKAKIBARA, Tasuku TAKEUCHI
  • Publication number: 20220240378
    Abstract: In multilayer circuit substrate wiring patterns and reference marks are formed on an upper surface of each insulating layer in a predetermined positional relationship, and the reference marks on the insulating layers are formed at overlapping positions when viewed from above. Furthermore, the reference mark on each layer is formed by changing a size or a shape such that from a specific edge portion recognized when center coordinates of the reference mark is detected by image processing a specific edge portion of the reference mark on a lower layer of the specific edge portion does not protrude considering a positional deviation at the time of manufacturing. The multiple insulating layers are formed of an insulating material having light transparency or an insulating material designed to be extremely thin so that a lower layer can be seen through even if the light transparency is poor.
    Type: Application
    Filed: June 13, 2019
    Publication date: July 28, 2022
    Applicant: FUJI CORPORATION
    Inventors: Tasuku TAKEUCHI, Ryojiro TOMINAGA
  • Publication number: 20220227043
    Abstract: A shaping method includes a first ejection step of ejecting a first curable viscous fluid, a planarization step of planarizing the first curable viscous fluid, a first curing step of curing the first curable viscous fluid, a cured layer forming step of repeatedly executing the first ejection step, the planarization step, and the first curing step to form a cured layer, a second ejection step of ejecting a second curable viscous fluid onto a surface of the cured layer, a second curing step of forming a smooth surface on the surface of the cured layer by curing the second curable viscous fluid, a third ejection step of ejecting a fluid containing metal particles onto the smooth surface, and a third curing step of curing the fluid containing the metal particles ejected in the third ejection step to form a metallic conductor on the smooth surface.
    Type: Application
    Filed: June 14, 2019
    Publication date: July 21, 2022
    Applicant: FUJI CORPORATION
    Inventors: Kenji TSUKADA, Tasuku TAKEUCHI, Ryojiro TOMINAGA
  • Publication number: 20210267054
    Abstract: A circuit formation method includes a wiring formation step of forming a wiring by applying a metal-containing liquid containing nanometer-sized metal fine particles onto a base and firing the metal-containing liquid, a paste application step of applying a resin paste containing micrometer-sized metal particles to be connected to the wiring formed in the wiring formation step, and a component placement step of placing a component having an electrode on the base, such that the electrode is in contact with the resin paste applied in the paste application step.
    Type: Application
    Filed: July 13, 2018
    Publication date: August 26, 2021
    Applicant: FUJI CORPORATION
    Inventors: Tasuku TAKEUCHI, Ryojiro TOMINAGA, Ryo SAKAKIBARA
  • Patent number: 11006529
    Abstract: A circuit forming method where a metal ink is ejected to a planned formation position of a first wiring at an upper face of a base material. Then, the metal ink is baked, and first wiring is formed. Further, a planned connection section of the first wiring and a second wiring is unbaked. The metal-ink is ejected over an upper face of the unbaked metal ink and a planned formation position of the second wiring at the upper face of the base material. Since the wettability of the upper face of the unbaked metal ink and the wettability of the upper face of the base material are equal to each other, the ejected metal ink ejected and the unbaked metal ink are not separated from each other, so that it is possible to properly connect the first wiring and the second wiring to each other.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 11, 2021
    Assignee: FUJI CORPORATION
    Inventors: Kenji Tsukada, Masatoshi Fujita, Yoshitaka Hashimoto, Tasuku Takeuchi, Akihiro Kawajiri, Masato Suzuki, Katsuaki Makihara
  • Publication number: 20190150292
    Abstract: A circuit forming method where a metal ink is ejected to a planned formation position of a first wiring at an upper face of a base material. Then, the metal ink is baked, and first wiring is formed. Further, a planned connection section of the first wiring and a second wiring is unbaked. The metal-ink is ejected over an upper face of the unbaked metal ink and a planned formation position of the second wiring at the upper face of the base material. Since the wettability of the upper face of the unbaked metal ink and the wettability of the upper face of the base material are equal to each other, the ejected metal ink ejected and the unbaked metal ink are not separated from each other, so that it is possible to properly connect the first wiring and the second wiring to each other.
    Type: Application
    Filed: June 28, 2016
    Publication date: May 16, 2019
    Applicant: FUJl CORPORATION
    Inventors: Kenji TSUKADA, Masatoshi FUJITA, Yoshitaka HASHIMOTO, Tasuku TAKEUCHI, Akihiro KAWAJIRI, Masato SUZUKI, Katsuaki MAKIHARA