Patents by Inventor Tasuku Tanaka

Tasuku Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140904
    Abstract: A compound represented by the following formula (1): One of R1 and R2 is a methyl group, and the other is an unsubstituted phenyl group, and R1 and R2 are not bonded to each other and therefore do not form a ring structure. One of R3 and R4 is a methyl group, and the other is an unsubstituted phenyl group, and R3 and R4 are not bonded to each other and therefore do not form a ring structure. R11 to R18, and R21 to R28 are hydrogen atoms, provided that, one selected from R11 to R18 is a single bond bonded to *a, and one selected from R21 to R28 is a single bond bonded to *b. L1 and L2 are each independently a single bond, or a substituted or unsubstituted phenylene group.
    Type: Application
    Filed: March 30, 2022
    Publication date: May 2, 2024
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Tasuku HAKETA, Shota TANAKA, Yusuke TAKAHASHI, Takuto FUKAMI, Tsukasa SAWATO
  • Publication number: 20240147846
    Abstract: An organic electroluminescent element including, an anode, a cathode, and an organic layer disposed between the anode and the cathode and including a light emitting zone. The organic layer includes a first layer containing a first compound and a second layer containing a second compound. The first layer and the second layer are different layers.
    Type: Application
    Filed: December 8, 2021
    Publication date: May 2, 2024
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Shota TANAKA, Shintaro BAN, Satomi TASAKI, Hiroaki ITOI, Tasuku HAKETA, Yuki NAKANO
  • Patent number: 11932785
    Abstract: The present invention provides an epoxy adhesive composition capable of reducing re-aggregation of an adhesive layer modifier, maintaining favorable viscosity for a long period of time, exhibiting high adhesiveness, and reducing process failures during application of the adhesive. Provided is an epoxy adhesive composition containing: a modified polyvinyl acetal resin having a constitutional unit with an acid-modified group; an adhesive layer modifier; and an epoxy resin, the epoxy adhesive composition having a ratio of an acid-modified group equivalent of the modified polyvinyl acetal resin to an epoxy equivalent of the epoxy resin (acid-modified group equivalent/epoxy equivalent) of 5.0 to 150.0, the epoxy adhesive composition having a number ratio of the acid-modified group to an epoxy group (acid-modified group number/epoxy group number) of 0.0005 to 0.5.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 19, 2024
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Tasuku Yamada, Shiori Tateno, Yousuke Chiba, Takayuki Maeda, Yukio Ochitani, Hideaki Tanaka
  • Patent number: 5519658
    Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: May 21, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Toshiro Hiramoto, Nobuo Tamba, Hisashi Ishida, Kazuhiro Akimoto, Masanori Odaka, Tasuku Tanaka, Jun Hirokawa, Masayuki Ohayashi
  • Patent number: 5360988
    Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: November 1, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Toshiro Hiramoto, Nobuo Tamba, Hisashi Ishida, Kazuhiro Akimoto, Masanori Odaka, Tasuku Tanaka, Jun Hirokawa, Masayuki Ohayashi
  • Patent number: 5223454
    Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: June 29, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda
  • Patent number: 5049972
    Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: September 17, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda