Patents by Inventor Tat Hin Tan
Tat Hin Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230361003Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: June 29, 2023Publication date: November 9, 2023Inventors: Bok Eng CHEAH, Choong Kooi CHEE, Jackson Chung Peng KONG, Wai Ling LEE, Tat Hin TAN
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Publication number: 20230253295Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: April 10, 2023Publication date: August 10, 2023Inventors: Bok Eng CHEAH, Choong Kooi CHEE, Jackson Chung Peng KONG, Wai Ling LEE, Tat Hin TAN
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Patent number: 11652026Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: GrantFiled: January 28, 2022Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
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Patent number: 11575383Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.Type: GrantFiled: February 6, 2021Date of Patent: February 7, 2023Assignee: SKYECHIP SDN BHDInventors: Chee Hak Teh, Yu Ying Ong, Wong Ging Yeon Mark, Tat Hin Tan, Soong Khim Chew
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Patent number: 11398415Abstract: Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.Type: GrantFiled: June 25, 2019Date of Patent: July 26, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Patent number: 11393741Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: GrantFiled: January 22, 2021Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
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Publication number: 20220208240Abstract: A generic physical layer providing a unified architecture for interfacing with an external memory device. The physical layer comprises a transmit data path for transmitting a parallel data to the external memory device and a receive data path for receiving a serial data from the external memory device. The generic physical layer is characterized by a receive enable logic for masking strobe of the serial data, wherein the transmit data path and the receive data path each comprising a FIFO circuit, a data rotator and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support.Type: ApplicationFiled: February 6, 2021Publication date: June 30, 2022Applicant: SKYECHIP SDN BHDInventors: Soon Chieh LIM, Chee Hak TEH, Tat Hin TAN
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Patent number: 11373694Abstract: A generic physical layer providing a unified architecture for interfacing with an external memory device. The physical layer comprises a transmit data path for transmitting a parallel data to the external memory device and a receive data path for receiving a serial data from the external memory device. The generic physical layer is characterized by a receive enable logic for masking strobe of the serial data, wherein the transmit data path and the receive data path each comprising a FIFO circuit, a data rotator and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support.Type: GrantFiled: February 6, 2021Date of Patent: June 28, 2022Assignee: SKYECHIP SDN BHDInventors: Soon Chieh Lim, Chee Hak Teh, Tat Hin Tan
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Publication number: 20220200610Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.Type: ApplicationFiled: February 6, 2021Publication date: June 23, 2022Applicant: SKYECHIP SDN BHDInventors: CHEE HAK TEH, YU YING ONG, Wong Ging Yeon MARK, Tat Hin TAN, Soong Khim CHEW
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Publication number: 20220157694Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Inventors: Bok Eng CHEAH, Choong Kooi CHEE, Jackson Chung Peng KONG, Wai Ling LEE, Tat Hin TAN
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Publication number: 20210320051Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: January 22, 2021Publication date: October 14, 2021Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee, Tat Hin Tan
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Patent number: 10903142Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: GrantFiled: May 3, 2019Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Patent number: 10714163Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.Type: GrantFiled: May 13, 2019Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Tat Hin Tan, Chee Hak Teh, Tick Sern Loh, Wilfred Wee Kee King, Yu Ying Ong
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Publication number: 20200091040Abstract: Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.Type: ApplicationFiled: June 25, 2019Publication date: March 19, 2020Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Publication number: 20200043831Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.Type: ApplicationFiled: May 3, 2019Publication date: February 6, 2020Inventors: Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Tat Hin Tan, Wai Ling Lee
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Publication number: 20190267062Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Applicant: Intel CorporationInventors: Tat Hin Tan, Chee Hak Teh, Tick Sern Loh, Wilfred Wee Kee King, Yu Ying Ong
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Patent number: 10333689Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.Type: GrantFiled: September 12, 2016Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Pankaj Vinayak Dudulwar, Chenchu Punnarao Bandi, Lip Khoon Teh, Tat Hin Tan
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Patent number: 10223483Abstract: A methodology for defining resistance-capacitance (RC) design targets based on radio-frequency (RF) simulation is provided. In particular, the method may involve first determining capacitance targets and then determining resistance targets. To compute the capacitance targets, integrate circuit design and simulations tools may run transient analysis to identify critical nodes, perform small signal and sensitivity analysis for the capacitance on the critical nodes, revise original RF specifications by allocating additional margin, and perform interpolation among multiple capacitance values to obtain capacitive design targets that meet the revised specifications.Type: GrantFiled: December 23, 2016Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Tat Hin Tan, William Walter Fergusson, Chieu Fung Tan
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Patent number: 10224911Abstract: An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.Type: GrantFiled: March 31, 2016Date of Patent: March 5, 2019Assignee: Altera CorporationInventors: Tat Hin Tan, Choong Kit Wong, Ker Yon Lau, Hsiao Wei Su, Hoong Chin Ng
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Patent number: 10200046Abstract: A delay-locked loop includes multiple inverters coupled together, wherein the inverters receive an input clock signal and output a first clock signal and a second clock signal. The input clock signal passes through a first set of inverters having a first number of inverters to generate the first clock signal. The input clock signal also passes through a second set of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal. The delay-locked loop also includes a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal.Type: GrantFiled: February 15, 2017Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Chee Seng Leong, Tat Hin Tan