Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract: A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination.

Abstract: A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination.

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract: A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination.

Abstract: A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Abstract: A network device includes an interface and packet processing logic. The interface receives a multicast packet. The packet processing logic determines identifier data corresponding to the received multicast packet and replicates the identifier data to multiple outgoing packet forward engines at a first point in a processing path. The packet processing logic further replicates the identifier data to multiple data streams at a second point in the processing path and replicates the identifier data to multiple logical interfaces in the same stream at a third point in the processing path.

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Abstract: A system for monitoring internal states of an integrated circuit includes logic nodes, selection logic and a monitor unit. The logic nodes are disposed within the integrated circuit and the selection logic is coupled to monitor pins externally accessible on the integrated circuit. The selection logic retrieves internal states of select logic nodes based on signals applied via the monitor pins. The monitor unit reads the internal states of the select logic nodes via the monitor pins.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.