Patents by Inventor Tatehito Kobayashi

Tatehito Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915951
    Abstract: A plasma processing apparatus includes a stage disposed in a processing chamber for mounting a wafer, a plasma generation chamber disposed above the processing chamber for plasma generation using process gas, a plate member having multiple introduction holes, made of a dielectric material, disposed above the stage and between the processing chamber and the plasma generation chamber, and a lamp disposed around the plate member for heating the wafer. The plasma processing apparatus further includes an external IR light source, an emission fiber arranged in the stage, that outputs IR light from the external IR light source toward a wafer bottom, and a light collection fiber for collecting IR light from the wafer. Data obtained using only IR light from the lamp is subtracted from data obtained also using IR light from the external IR light source during heating of the wafer. Thus, a wafer temperature is determined.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 27, 2024
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Hiroyuki Kobayashi, Nobuya Miyoshi, Kazunori Shinoda, Tatehito Usui, Naoyuki Kofuji, Yutaka Kouzuma, Tomoyuki Watanabe, Kenetsu Yokogawa, Satoshi Sakai, Masaru Izawa
  • Publication number: 20220149235
    Abstract: A first semiconductor device of an embodiment of the present disclosure includes: a semiconductor substrate having one surface and another surface opposed to each other, and having a side length of 50 ?m or more and 500 ?m or less; a single or multiple bumps provided on the other surface; and a projection-and-depression structure formed in a side surface of the semiconductor substrate.
    Type: Application
    Filed: February 7, 2020
    Publication date: May 12, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tatehito KOBAYASHI
  • Patent number: 7524684
    Abstract: A semiconductor device is formed by bonding bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: April 28, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Tatehito Kobayashi
  • Publication number: 20080241977
    Abstract: A semiconductor device is formed by bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead.
    Type: Application
    Filed: September 10, 2007
    Publication date: October 2, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Tatehito Kobayashi
  • Publication number: 20080009083
    Abstract: A semiconductor device is formed by bonding bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead.
    Type: Application
    Filed: September 10, 2007
    Publication date: January 10, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Tatehito Kobayashi
  • Patent number: 7279706
    Abstract: A semiconductor device is formed by bonding bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tatehito Kobayashi
  • Publication number: 20050073056
    Abstract: A semiconductor device is formed by bonding bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead.
    Type: Application
    Filed: October 6, 2004
    Publication date: April 7, 2005
    Inventor: Tatehito Kobayashi