Abstract: A sensor module for measuring a concentration of a gas by utilizing changes in an amount of absorbed light includes a light emitting device and a light receiving device configured to receive light emitted by the light emitting device, wherein the light emitting device and the light receiving device are disposed to face each other across a gap, wherein the light emitting device and the light receiving device are positioned such as to be exposed to the gas, and the gap forms part of a flow pathway of the gas, and wherein the gap is greater than or equal to 0.2 mm and less than or equal to 1.0 mm.

Abstract: An electronic device includes: a support body including first and second planar portions facing each other, a first connecting portion connecting the first and second planar portions, and a first receptacle surrounded by the first and second planar portions and the first connecting portion; a projection being part of the second planar portion projecting outward from the first receptacle outside the first planar portion in plan view; a wiring substrate including a facing surface facing the support body and an opposite surface opposite to the facing surface, the wiring substrate being folded and attached along an inner surface of the first receptacle and a surface of the projection continuous with the inner surface of the first receptacle; a sensor element mounted on the facing surface attached to the inner surface of the first receptacle; and an antenna mounted on the opposite surface attached to the surface of the projection.

Abstract: A sensor module for measuring a concentration of a gas by utilizing changes in an amount of absorbed light includes a light emitting device and a light receiving device configured to receive light emitted by the light emitting device, wherein the light emitting device and the light receiving device are disposed to face each other across a gap, wherein the light emitting device and the light receiving device are positioned such as to be exposed to the gas, and the gap forms part of a flow pathway of the gas, and wherein the gap is greater than or equal to 0.2 mm and less than or equal to 1.0 mm.

Abstract: A semiconductor device includes an antenna mounted on a wiring substrate. A holding member includes a first plate-shaped part having a first surface and a second surface, a second plate-shaped part having a third surface and a fourth surface, and a coupling part configured to couple the first plate-shaped part and the second plate-shaped part so that the second surface and the third surface have parts facing each other with a space therebetween. The one end of the wiring substrate is fixed to the holding member so that the antenna overlaps the coupling part, as seen from above. A part continuing to the one end of the wiring substrate is folded back so as to being arranged sequentially along the first surface, the second surface, the third surface, and the fourth surface. The other end of the wiring substrate extends in an elastically deformable state from the fourth surface.

Abstract: An electronic device includes: a support body including first and second planar portions facing each other, a first connecting portion connecting the first and second planar portions, and a first receptacle surrounded by the first and second planar portions and the first connecting portion; a projection being part of the second planar portion projecting outward from the first receptacle outside the first planar portion in plan view; a wiring substrate including a facing surface facing the support body and an opposite surface opposite to the facing surface, the wiring substrate being folded and attached along an inner surface of the first receptacle and a surface of the projection continuous with the inner surface of the first receptacle; a sensor element mounted on the facing surface attached to the inner surface of the first receptacle; and an antenna mounted on the opposite surface attached to the surface of the projection.

Abstract: A protection circuit module includes an insulating substrate, a first surge withstand chip resistor mounted on a pair of first pads formed on one surface of the insulating substrate, a second surge withstand chip resistor mounted on a pair of second pads formed on the other surface of the insulating substrate, and arranged at a position on the other surface of the insulating substrate overlapping the first surge withstand chip resistor in a plan view, a first wiring coupled to one first pad, a second wiring coupled to one second pad, a third wiring coupling the other first pad and the other second pad to the same potential, and a shield wiring provided on an inner layer of the insulating substrate and arranged in a region in which at least the one first pad and the one second pad oppose each other.

Abstract: A semiconductor device includes an antenna mounted on a wiring substrate. A holding member includes a first plate-shaped part having a first surface and a second surface, a second plate-shaped part having a third surface and a fourth surface, and a coupling part configured to couple the first plate-shaped part and the second plate-shaped part so that the second surface and the third surface have parts facing each other with a space therebetween. The one end of the wiring substrate is fixed to the holding member so that the antenna overlaps the coupling part, as seen from above. A part continuing to the one end of the wiring substrate is folded back so as to being arranged sequentially along the first surface, the second surface, the third surface, and the fourth surface. The other end of the wiring substrate extends in an elastically deformable state from the fourth surface.

Abstract: A protection circuit module includes an insulating substrate, a first surge withstand chip resistor mounted on a pair of first pads formed on one surface of the insulating substrate, a second surge withstand chip resistor mounted on a pair of second pads formed on the other surface of the insulating substrate, and arranged at a position on the other surface of the insulating substrate overlapping the first surge withstand chip resistor in a plan view, a first wiring coupled to one first pad, a second wiring coupled to one second pad, a third wiring coupling the other first pad and the other second pad to the same potential, and a shield wiring provided on an inner layer of the insulating substrate and arranged in a region in which at least the one first pad and the one second pad oppose each other.

Abstract: A circuit board includes a rigid board including a first wiring layer formed on its upper surface side, and a flexible board including a base material having flexibility and disposed on an upper surface side of the first wiring layer, a second wiring layer formed on the base material, and a via wiring formed in a through-hole passing through the second wiring layer and the base material. The via wiring has a protrusion protruding from an upper surface of the second wiring layer, and extending on the upper surface of the second wiring layer positioned on an outer circumferential side of the through-hole.

Abstract: A wiring substrate includes an insulating layer, at least one via hole formed in the insulating layer, a first wiring layer formed on one surface of the insulating layer and having a droop portion at an end-side of the via hole, a second wiring layer formed on the other surface of the insulating layer, and a metal-plated layer formed in the via hole and configured to connect the second wiring layer and the droop portion of the first wiring layer. One surface of the insulating layer around the via hole is formed as a convex curved surface and the droop portion of the first wiring layer is arranged on the convex curved surface.

Abstract: A circuit board includes a rigid board including a first wiring layer formed on its upper surface side, and a flexible board including a base material having flexibility and disposed on an upper surface side of the first wiring layer, a second wiring layer formed on the base material, and a via wiring formed in a through-hole passing through the second wiring layer and the base material. The via wiring has a protrusion protruding from an upper surface of the second wiring layer, and extending on the upper surface of the second wiring layer positioned on an outer circumferential side of the through-hole.

Abstract: A wiring substrate includes an insulating layer, a first wiring layer and a second wiring layer on opposite sides of the insulating layer, and a via piercing through the first wiring layer and the insulating layer to electrically connect to the second wiring layer. The via includes an end portion projecting from a first surface of the first wiring layer facing away from the insulating layer. A surface of the end portion facing in the same direction as the first surface of the first wiring layer is depressed to be deeper in the center than in the periphery.

Abstract: An inductor device includes a first insulating layer having a first via hole, a first metal layer formed on an upper surface of the first insulating layer and having a droop portion at an upper end-side of the first via hole, a second metal layer formed on a lower surface of the first insulating layer and having a first connection part exposed to a bottom surface of the first via hole, and a first metal-plated layer formed in the first via hole and configured to connect the first connection part and the droop portion of the first metal layer.

Abstract: A wiring substrate includes an insulating layer, a first wiring layer and a second wiring layer on opposite sides of the insulating layer, and a via piercing through the first wiring layer and the insulating layer to electrically connect to the second wiring layer. The via includes an end portion projecting from a first surface of the first wiring layer facing away from the insulating layer. A surface of the end portion facing in the same direction as the first surface of the first wiring layer is depressed to be deeper in the center than in the periphery.

Abstract: An inductor device includes a first insulating layer having a first via hole, a first metal layer formed on an upper surface of the first insulating layer and having a droop portion at an upper end-side of the first via hole, a second metal layer formed on a lower surface of the first insulating layer and having a first connection part exposed to a bottom surface of the first via hole, and a first metal-plated layer formed in the first via hole and configured to connect the first connection part and the droop portion of the first metal layer.

Abstract: A wiring substrate includes an insulating layer, at least one via hole formed in the insulating layer, a first wiring layer formed on one surface of the insulating layer and having a droop portion at an end-side of the via hole, a second wiring layer formed on the other surface of the insulating layer, and a metal-plated layer formed in the via hole and configured to connect the second wiring layer and the droop portion of the first wiring layer. One surface of the insulating layer around the via hole is formed as a convex curved surface and the droop portion of the first wiring layer is arranged on the convex curved surface.

Abstract: A wiring substrate includes a heat radiation plate and a substrate provided on the heat radiation plate interposed by an adhesive layer. The substrate includes a first surface on which the adhesive layer is provided and a second surface on an opposite side of the first surface. The wiring substrate also includes a wiring provided on the second surface of the substrate, and a notch part that penetrates the substrate in a thickness direction of the substrate, with the notch part being formed by notching the wiring substrate inward from an outer edge part of the substrate from a plan view. The adhesive layer covers an end surface of the substrate that is exposed in an inner wall surface of the notch part.

Abstract: A wiring substrate includes a heat sink, an insulation layer, first and second wiring layers, first and second through wirings, and first and second pads. The insulation layer is arranged on the heat sink with an adhesive layer located in between. The insulation layer includes first and second through holes. The first and second wiring layers are arranged on a surface of the insulation layer in contact with the adhesive layer. The first and second wiring layers are embedded in the adhesive layer. The first through wiring formed in the first through hole is connected to the first wiring layer and thermally coupled to the semiconductor device. The second through wiring formed in the first through hole is connected to the second wiring layer and electrically connected to the semiconductor device. The pads cover exposed surfaces of the through wirings.

Abstract: A wiring substrate includes a heat spreader, a first insulating layer provided on the heat spreader via an adhesion layer, the first insulating layer, a plurality of through wirings formed to fill through holes provided at the first insulating layer, respectively, a thermal diffusion wiring provided on the first insulating layer so as to be connected to the through wirings, the thermal diffusion wiring being configured not to be electrically connected to a semiconductor device, an electrical connection wiring provided on the first insulating layer, the electrical connection wiring being configured to be electrically connected to the semiconductor device, wherein the heat spreader is provided with a projection portion, made of a composition same as the heat spreader, at a surface of the heat spreader on which the adhesion layer is formed, the projection portion being aimed at least at an area overlapping the through wirings in a plan view.

Abstract: A wiring substrate for a semiconductor device includes a heat spreader; a polyimide layer provided with through holes and provided on the heat spreader via an adhesion layer; through wirings formed to fill the through holes of the polyimide layer; a thermal diffusion wiring provided on the polyimide layer and is configured not to be electrically connected to the semiconductor device; an electrical connection wiring provided on the polyimide layer at a same plane with the thermal diffusion wiring and is configured to be electrically connected to the semiconductor device; and an insulating layer provided on the polyimide layer with a first open portion and a second open portion that expose the electrical connection wiring and the thermal diffusion wiring, respectively, the thermal diffusion wiring being formed to extend at an outer side of the second open portion and have a larger area than the electrical connection wiring.