Abstract: Disclosed is a symbol timing recovery circuit which includes an interpolator to generate, using a first filter, interpolation data of an input signal; a forward equalizer to eliminate, using a second filter, a forward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a first identification signal, and a first error signal; a backward equalizer to eliminate, using a third filter, a backward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a second identification signal, and a second error signal; and a timing recovery unit to generate a tap coefficient of the first filter, based on a tap coefficient of the second filter, a tap coefficient of the third filter, the first identification signal, the first error signal, the second identification signal, and the second error signal.

Abstract: Disclosed is a symbol timing recovery circuit which includes an interpolator to generate, using a first filter, interpolation data of an input signal; a forward equalizer to eliminate, using a second filter, a forward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a first identification signal, and a first error signal; a backward equalizer to eliminate, using a third filter, a backward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a second identification signal, and a second error signal; and a timing recovery unit to generate a tap coefficient of the first filter, based on a tap coefficient of the second filter, a tap coefficient of the third filter, the first identification signal, the first error signal, the second identification signal, and the second error signal.

Abstract: An analog-to-digital (A/D) converter samples an input signal with a first clock. An finite impulse response (FIR) filter generates data at a zero-crossing point/data decision point from the sampled data. A decimation circuit decimates an output of the FIR filter 2 with a second clock. A phase comparator detects a phase error of the output signal of the decimation circuit. An Numerically Controlled Oscillator (NCO) (A/D) generates a phase signal by integrating the phase error. A tap coefficient computing unit generates tap coefficients of the FIR filter in accordance with the phase signal. In the NCO, if the phase signal exceeds “?”, “2?+the phase error” is subtracted from the phase signal.

Abstract: A demodulation circuit can perform a capturing operation although a frequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.

Abstract: An A/D converter samples an input signal with a first clock. An FIR filter generates data at a zero-crossing point/data decision point from the sampled data. A decimation circuit decimates an output of the FIR filter 2 with a second clock. A phase comparator detects a phase error of the output signal of the decimation circuit. An NCO generates a phase signal by integrating the phase error. A tap coefficient computing unit generates tap coefficients of the FIR filter in accordance with the phase signal. In the NCO, if the phase signal exceeds “?”, “2?+ the phase error” is subtracted from the phase signal.

Abstract: An equalizer comprises: a calculation unit performing calculation of a tap coefficient for each symbol interval; an interpolation unit obtaining, by performing interpolation, a tap coefficient that has become necessary due to oversampling, including a tap coefficient of a symbol interval, by using a tap coefficient of the symbol interval output from the calculation unit; a filter unit performing equalization on an input signal by using the tap coefficient obtained by the interpolation unit; and a thinning unit thinning data of a sampling interval output from the filter unit into data of the symbol interval to be used as output from the oversampling transversal equalizer.

Abstract: A demodulation circuit according to the present invention comprises an automatic equalizer for carrying out equalization processing of a signal, a carrier recovery circuit for carrying out carrier recovery processing based on an equalized signal by the automatic equalizer. A center tap for carrying out an amplitude control of the automatic equalizer is placed on an input side thereof, and a control signal to the center tap is transmitted from the automatic equalizer.

Abstract: A demodulation circuit can perform a capturing operation although afrequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.

Abstract: In a radio communication device which generates a baseband signal based on inputted transmit data, then modulates the baseband signal to a modulating signal, amplifies the modulating signal in a modulating circuit, and transmits the amplified modulating signal, a modulating signal control circuit which detects an amplitude of the modulating signal based on a digital baseband signal before DA conversion processing generated in a baseband processing circuit and controls a dynamic range of the amplification circuit based on a result of the detection is provided, and consequently, the amplification circuit can be properly controlled according to the state of a transmit signal by a simple circuit configuration.

Abstract: A symbol timing recovery circuit of the type that controls the phase of a received signal to synchronize it to a clock is capable of accommodating differing symbol rates. Base clock frequency fsamp is divided by N to derive frequency fsamp′, where N is the largest integer contained in a set of integers by any of which the base frequency fsamp can be divided to derive a frequency more than twice as high as symbol rate fs, and sampling clock CLK3 of the frequency fsamp′is used in an FIR filter 20. &Dgr;th is added to the output of a loop filter 38, and the result is supplied to an NCO 42. The value of &Dgr;th is determined from the difference between 2fs and fsamp′.

Abstract: According to the present invention, in accordance with the first to fourth quadrants on the phase plane for signal points, a phase angle detector converts an I channel signal or a Q channel signal obtained by a demodulator, by using individually set operating expressions, so as to correlate the angle (phase angle) for a signal point on the plane phase with a predetermined one-dimensional coordinate. More specifically, the phase angle that extends from a border point in an arbitrary quadrant on the phase plane to a border position shifted 360° is allocated for a specific one-dimensional coordinate. The coordinate value on the one-dimensional coordinate is calculated by using the operating expression which is set in accordance with the first to the fourth quadrant of the signal point which is detected using the I channel signal and the Q channel signal.

Abstract: A monostable multivibrating circuit includes: a time constant setting circuit responsive to an input pulse signal, for outputting at least one signal having a time constant different from that of the input pulse signal; and an emitter-coupled logic circuit including a first pair of transistors, one base receiving the input pulse signal and another base receiving a first reference signal, and a second pair of transistors, one base receiving an output signal of the time constant setting circuit and another base receiving a second reference signal. The monostable multivibrating circuit outputs a one-shot pulse defined by a pulse starting time corresponding to a change in level of the one base input of the first pair of transistors and a pulse stopping time corresponding to a change in level of the one base input of the second pair of transistors.