Patents by Inventor Tatsuaki Kuji

Tatsuaki Kuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6845042
    Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: January 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Koji Hashimoto, Tatsuaki Kuji, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Koji Sakui
  • Publication number: 20040152262
    Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
    Type: Application
    Filed: February 6, 2003
    Publication date: August 5, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Koji Hashimoto, Tatsuaki Kuji, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Koji Sakui
  • Patent number: 6727026
    Abstract: In a method of designing patterns of a semiconductor integrated circuit, the shape of each of a plurality of opening patterns formed by a plurality of contact holes is formed into a rectangular shape; and the contact holes are arranged in such a manner that a long side of each of the rectangular opening patterns is opposite to a long side of an adjacent rectangular opening pattern, and the positions of both ends of the long sides are trued up. Furthermore, a photomask is used for manufacturing a semiconductor integrated circuit as designed by the above method of designing patterns of a semiconductor integrated circuit, in which a plurality of rectangular opening patterns are provided thereon as a plurality of rectangular opening patterns for contact holes; and the a plurality of rectangular opening patterns are arranged in such a manner that adjacent long sides thereof are opposite to each other, and the position of both ends of each long side is trued up.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: April 27, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuaki Kuji, Koji Hashimoto, Satoshi Usui, Shigeki Nojima
  • Publication number: 20010024758
    Abstract: In a method of designing patterns of a semiconductor integrated circuit, the shape of each of a plurality of opening patterns formed by a plurality of contact holes is formed into a rectangular shape; and the contact holes are arranged in such a manner that a long side of each of the rectangular opening patterns is opposite to a long side of an adjacent rectangular opening pattern, and the positions of both ends of the long sides are trued up. Furthermore, a photomask is used for manufacturing a semiconductor integrated circuit as designed by the above method of designing patterns of a semiconductor integrated circuit, in which a plurality of rectangular opening patterns are provided thereon as a plurality of rectangular opening patterns for contact holes; and the a plurality of rectangular opening patterns are arranged in such a manner that adjacent long sides thereof are opposite to each other, and the position of both ends of each long side is trued up.
    Type: Application
    Filed: March 23, 2001
    Publication date: September 27, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuaki Kuji, Koji Hashimoto, Satoshi Usui, Shigeki Nojima