Patents by Inventor Tatsuhiko Amagai
Tatsuhiko Amagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120051367Abstract: Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: JUNIPER NETWORKS, INC.Inventors: Tatsuhiko Amagai, Yuichi Suzuki
-
Patent number: 8073006Abstract: Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.Type: GrantFiled: June 30, 2005Date of Patent: December 6, 2011Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Yuichi Suzuki
-
Patent number: 7970012Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: GrantFiled: February 27, 2009Date of Patent: June 28, 2011Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Mikiharu Yamashita, Tatsuo Aramizu
-
Publication number: 20090161694Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: ApplicationFiled: February 27, 2009Publication date: June 25, 2009Applicant: JUNIPER NETWORKS, INC.Inventors: Tatsuhiko AMAGAI, Mikiharu YAMASHITA, Tatsuo ARAMIZU
-
Patent number: 7515610Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: GrantFiled: September 29, 2006Date of Patent: April 7, 2009Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Mikiharu Yamashita, Tatsuo Aramizu
-
Publication number: 20070025380Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: ApplicationFiled: September 29, 2006Publication date: February 1, 2007Applicant: JUNIPER NETWORKS, INC.Inventors: Tatsuhiko AMAGAI, Mikiharu YAMASHITA, Tatsuo ARAMIZU
-
Patent number: 7130312Abstract: A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.Type: GrantFiled: September 24, 1999Date of Patent: October 31, 2006Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Mikiharu Yamashita, Tatsuo Aramizu
-
Publication number: 20060002396Abstract: Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.Type: ApplicationFiled: June 30, 2005Publication date: January 5, 2006Inventors: Tatsuhiko Amagai, Yuichi Suzuki
-
Patent number: 6944182Abstract: Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.Type: GrantFiled: May 10, 2000Date of Patent: September 13, 2005Assignee: Juniper Networks, Inc.Inventors: Tatsuhiko Amagai, Yuichi Suzuki
-
Patent number: 6687250Abstract: A device with quality controllable SAR function according to upper layer instruction enables reassembly and segmentation SAR of AAL5 to which priority in upper layer is reflected to be provided in reassembly and segmentation of AAL5 in ATM layer processing.Type: GrantFiled: May 26, 2000Date of Patent: February 3, 2004Assignee: NEC CorporationInventors: Yuichi Suzuki, Tatsuhiko Amagai
-
Publication number: 20030231633Abstract: Even when a communication failure happens to occur, the interrupted communication can be quickly recovered by a router apparatus. The router apparatus is comprised of: a plurality of routing tables into which new route information is stored every time route information is changed; a rewriting time saving unit for saving rewriting time information of the plurality of routing tables; a table switching unit for switching the plurality of routing tables; and a route processor unit for managing, for example, setting/rewriting/deleting the routing table based upon route information supplied by a network operator, or route information obtained by routing protocol.Type: ApplicationFiled: June 24, 2003Publication date: December 18, 2003Applicant: NEC CORPORATIONInventors: Tatsuo Aramizu, Tatsuhiko Amagai, Hiroshi Ikeda
-
Patent number: 6625659Abstract: Even when a communication failure happens to occur, the interrupted communication can be quickly recovered by a router apparatus. The router apparatus is comprised of: a plurality of routing tables into which new route information is stored every time route information is changed; a rewriting time saving unit for saving rewriting time information of the plurality of routing tables; a table switching unit for switching the plurality of routing tables; and a route processor unit for managing, for example, setting/rewriting/deleting the routing table based upon route information supplied by a network operator, or route information obtained by routing protocol.Type: GrantFiled: January 18, 2000Date of Patent: September 23, 2003Assignee: NEC CorporationInventors: Tatsuo Aramizu, Tatsuhiko Amagai, Hiroshi Ikeda
-
Patent number: 6515998Abstract: A table data retrieving apparatus comprises a plurality of tables in which a reference data is stored. Each table of said plurality of tables is allocated into any group of a plurality of groups. A management table stores a priority of said table. A data retrieving section selects a group based on the retrieving key by which the reference data is selected. The data retrieving section retrieves with the priority said table which is allocated into the selected group is stored.Type: GrantFiled: November 16, 1999Date of Patent: February 4, 2003Assignee: NEC CorporationInventors: Mikiharu Yamashita, Tatsuhiko Amagai, Tatsuo Aramizu
-
Patent number: 6493356Abstract: A segment and reassembly system cooperates with a data processing system for various kinds of data processing on ATM cells accumulated in frame buffers, and supplies ATM cells to ISDN after completion of various kinds of data processing; wherein the segment and reassembly system has processing units connected through exclusive interfaces to engines incorporated in the data processing system, and the engines process the pieces of data stored in the frame buffers at high speed, thereby improving the throughput of the segmentation and reassembly system.Type: GrantFiled: January 7, 1999Date of Patent: December 10, 2002Assignee: NEC CorporationInventors: Tatsuo Aramizu, Tatsuhiko Amagai, Yasuo Hamakawa, Kazuhiko Isoyama
-
Patent number: 6418145Abstract: An internet protocol (IP) layer processor has an IP header processing section for checking a defect in an IP header of a first ATM cell of an AAL5 frame, and a SAR (segregation and reassemblage) section for transferring the AAL5 frame in the form of separate ATM cells if the check by the IP header processing section indicates a normal IP header, without using a CPU. SAR notifies a defect in the IP header to CPU without transmission of the AAL5 frame if the check indicates the defect in the IP header. The IP layer processor achieves a higher processing due to the direct transfer by the SAR without using processing by a software.Type: GrantFiled: December 17, 1998Date of Patent: July 9, 2002Assignee: NEC CorporationInventors: Kazuhiko Isoyama, Tatsuhiko Amagai, Toshiya Aramaki