Patents by Inventor Tatsuhiko Aoki
Tatsuhiko Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230243062Abstract: A silicon wafer is provided which is a Czochralski wafer formed of silicon, and a method for producing the silicon wafer are provided. The wafer includes a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.Type: ApplicationFiled: June 14, 2021Publication date: August 3, 2023Inventors: Haruo SUDO, Takashi ISHIKAWA, Koji IZUNOME, Hisashi MATSUMURA, Tatsuhiko AOKI, Shoji IKEDA, Tetsuo ENDOH, Etsuo FUKUDA
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Publication number: 20220319835Abstract: The occurrence of breaking and chipping at the wafer peripheral edge of a bonded wafer obtained by bonding a lamination wafer on a support wafer is suppressed. A lamination wafer to be bonded to a support wafer includes a large-diameter portion made of a silicon wafer whose peripheral edge is chamfered and a small-diameter portion, whose diameter is smaller than that of the large-diameter portion, formed on the large-diameter portion concentrically and integrally with the large-diameter portion, and the small-diameter portion includes a straight body portion whose side surface is perpendicular to the wafer surface, and a neck portion whose side surface is oblique with a predetermined angle to the wafer between the straight body portion and the large-diameter portion, and the small-diameter portion is formed such that the upper face of the straight body portion is to be bonded to the support wafer.Type: ApplicationFiled: July 27, 2020Publication date: October 6, 2022Applicant: GLOBALWAFERS JAPAN CO., LTD.Inventors: Tatsuhiko AOKI, Manabu HIRASAWA
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Publication number: 20210348302Abstract: Provided is a method for heat-treating a silicon wafer in an inert gas atmosphere, wherein it is possible to discharge SiO gas produced in melting a natural oxide film on the surface of the silicon wafer efficiently, to suppress the accumulation of reaction products in the heat treatment chamber, and to prevent slip deterioration. The wafer is held for a period of 5 to 30 sec inclusive, the rotational speed of the wafer is set to 80 to 120 rpm, and further the inert gas supply in the chamber is controlled so that the gas replacement rate is 90% or more in a temperature range of 900 to 1100° C. inclusive.Type: ApplicationFiled: October 10, 2019Publication date: November 11, 2021Applicant: GLOBALWAFERS JAPAN CO., LTD.Inventors: Aya USHIODA, Tatsuhiko AOKI
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Patent number: 10840089Abstract: A protective-film forming method for a semiconductor substrate suppresses deterioration in the number of LPDs and adhesion of impurities such as particles by forming a new protective-film of a surfactant solution when the semiconductor substrate is detached from a polishing head. The method includes a first protective-film forming process for forming a protective-film by hydrophilizing the front surface of the polished substrate with a surfactant solution and, after the first protective-film forming process, a second protective-film forming process for forming protective-films on the front and back surface of the substrate by detaching the substrate from the polishing head in a state where at least the front surface of the polished semiconductor substrate is in contact with the liquid surface of the protective-film forming treatment liquid comprising a surfactant solution, then by immersing the polished substrate in a protective-film forming treatment liquid.Type: GrantFiled: February 3, 2017Date of Patent: November 17, 2020Assignee: GLOBALWAFERS JAPAN CO., LTD.Inventors: Shin Sakai, Hiroaki Kariyazaki, Tatsuhiko Aoki, Koji Araki
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Publication number: 20200203159Abstract: A protective-film forming method for a semiconductor substrate suppresses deterioration in the number of LPDs and adhesion of impurities such as particles by forming a new protective-film of a surfactant solution when the semiconductor substrate is detached from a polishing head. The method includes a first protective-film forming process for forming a protective-film by hydrophilizing the front surface of the polished substrate with a surfactant solution and, after the first protective-film forming process, a second protective-film forming process for forming protective-films on the front and back surface of the substrate by detaching the substrate from the polishing head in a state where at least the front surface of the polished semiconductor substrate is in contact with the liquid surface of the protective-film forming treatment liquid comprising a surfactant solution, then by immersing the polished substrate in a protective-film forming treatment liquid.Type: ApplicationFiled: February 3, 2017Publication date: June 25, 2020Applicant: GLOBALWAFERS JAPAN CO., LTD.Inventors: Shin SAKAI, Hiroaki KARIYAZAKI, Tatsuhiko AOKI, Koji ARAKI
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Patent number: 10141180Abstract: A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [?m] which is calculated according to the below equations (1) to (3): X [?m]=a [?m]+b [?m]??(1); a [?m]=(0.0031×(said maximum temperature) [° C.]?3.1)×6.4×(cooling rate)?0.4 [° C./second]??(2); and b [?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]??(3).Type: GrantFiled: July 31, 2014Date of Patent: November 27, 2018Assignee: GLOBALWAFERS JAPAN CO., LTD.Inventors: Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Takeshi Senda
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Publication number: 20160293446Abstract: Provided is a method for manufacturing a silicon wafer including a first step of heat-treating a raw silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method in an oxidizing gas atmosphere at a maximum target temperature of 1300 to 1380° C., a second step of removing an oxide film on a surface of the heated-treated silicon wafer obtained in the first step, and a third step of heat-treating the stripped silicon wafer obtained in the second step in a non-oxidizing gas atmosphere at a maximum target temperature of 1200 to 1380° C. and at a heating rate of 1° C./sec to 150° C./sec in order that the silicon wafer may have a maximum oxygen concentration of 1.3×1018 atoms/cm3 or below in a region from the surface up to 7 ?m in depth.Type: ApplicationFiled: March 28, 2016Publication date: October 6, 2016Applicant: GlobalWafers Japan Co., Ltd.Inventors: Haruo SUDO, Koji ARAKI, Tatsuhiko AOKI, Susumu MAEDA
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Patent number: 8999864Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.Type: GrantFiled: May 28, 2010Date of Patent: April 7, 2015Assignee: Global Wafers Japan Co., Ltd.Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
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Publication number: 20150044422Abstract: A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [?m] which is calculated according to the below equations (1) to (3): X[?m]=a[?m]+b[?m]??(1); a[?m]=(0.0031×(said maximum temperature)[° C.]?3.1)×6.4×(cooling rate)?0.4[° C./second] . . . (2); and b[?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]??(3).Type: ApplicationFiled: July 31, 2014Publication date: February 12, 2015Inventors: Koji ARAKI, Tatsuhiko AOKI, Haruo SUDO, Takeshi SENDA
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Patent number: 8476149Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.Type: GrantFiled: July 30, 2009Date of Patent: July 2, 2013Assignee: Global Wafers Japan Co., Ltd.Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
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Publication number: 20130078588Abstract: A method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD density along a diameter of a bulk of the wafer grown by the CZ process can be improved. Further, a method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD size can also be improved and COP of a surface layer of the wafer can be reduced. The method includes a step of a first heat treatment in which the CZ silicon wafer is heated to a temperature from 1325 to 1400° C. in an oxidizing gas atmosphere, held at the temperature, and then cooled at a cooling rate of from 50 to 250° C./second, and a step of a second heat treatment in which the wafer is heated to a temperature from 900 to 1200° C. in a non-oxidizing gas atmosphere, held at the temperature, and then cooled.Type: ApplicationFiled: September 25, 2012Publication date: March 28, 2013Applicant: Covalent Silicon CorporationInventors: Takeshi Senda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Susumu Maeda
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Patent number: 8399341Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.Type: GrantFiled: May 17, 2010Date of Patent: March 19, 2013Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Patent number: 8252700Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.Type: GrantFiled: January 21, 2010Date of Patent: August 28, 2012Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20120184091Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.Type: ApplicationFiled: May 17, 2010Publication date: July 19, 2012Applicant: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20120139088Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.Type: ApplicationFiled: May 28, 2010Publication date: June 7, 2012Applicant: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
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Publication number: 20100197146Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.Type: ApplicationFiled: January 21, 2010Publication date: August 5, 2010Applicant: COVALENT MATERIALS CORPORATIONInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20100038757Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.Type: ApplicationFiled: July 30, 2009Publication date: February 18, 2010Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
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Publication number: 20080237190Abstract: A surface cleaning method of a semiconductor wafer heat treatment boat that can prevent metallic contamination to semiconductor wafers and keep down a production time and manufacturing costs of semiconductor wafers by efficiently and easily removing metallic impurities in an oxide film on an SiC boat surface is provided. A surface cleaning method of a semiconductor wafer heat treatment boat according to an embodiment of the present invention is a surface cleaning method of a semiconductor wafer heat treatment boat whose surface is formed of SiC, includes oxidizing the surface of the heat treatment boat by thermal oxidation and etching a portion of the oxide film formed after oxidation is removed.Type: ApplicationFiled: September 26, 2007Publication date: October 2, 2008Applicant: Covalent Materials CorporationInventors: Tatsuhiko Aoki, Motohiro Sei, Koji Araki
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Publication number: 20080166891Abstract: The present invention provides a heat treatment method for a silicon wafer in which, with respect to a surface of the silicon wafer made flat at an atomic level by a high-temperature heat-treatment at 1,100° C. or more, a surface roughness of the wafer can be reduced compared with the conventional one while maintaining a step terrace structure on the surface of the above-mentioned wafer, and the surface of such a wafer can be formed stably. In the heat treatment method for the silicon wafer in which the step terrace structure is formed on the surface of the silicon wafer, after the silicon wafer is heat treated at 1,100° C. or more in a heat treatment furnace in a reducing gas or inert gas atmosphere, the atmosphere in the furnace is arranged to be of argon gas at a temperature of 500° C.Type: ApplicationFiled: December 27, 2007Publication date: July 10, 2008Inventors: Manabu Hirasawa, Koji Izunome, Koji Araki, Tatsuhiko Aoki
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Publication number: 20070065269Abstract: This invention intends to provide a coiled carrying article pallet, which is suited for transporting small quantities of varied types of articles, which can easily, deliberately, efficiently transporting a coiled carrying article to a transport receptacle without damaging the coiled transport article, which can transport the coiled carrying article with transport cost being held down, and which can improve space efficiency for storage, and the like.Type: ApplicationFiled: February 7, 2003Publication date: March 22, 2007Inventors: Tatsuhiko Aoki, Nobuaki Itou, Nobuhiro Kato