Patents by Inventor Tatsuhiko Fijihira

Tatsuhiko Fijihira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6528826
    Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p31 well region, an n− depletion region formed in the surface layer of the p− well region, to extend from the n+ emitter region to a surface layer of the n− drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: March 4, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuhiko Yoshida, Motoi Kudoh, Tatsuhiko Fijihira
  • Patent number: 6268628
    Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p− well region, an n− depletion region formed in the surface layer of the p well region, to extend from the n+ emitter region to a surface layer of the n drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: July 31, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuhiko Yoshida, Motoi Kudoh, Tatsuhiko Fijihira