Patents by Inventor Tatsuhiko Higashiki

Tatsuhiko Higashiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9922991
    Abstract: A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya Kamigaki, Isahiro Hasegawa, Shinichi Ito, Soichi Inoue, Tatsuhiko Higashiki, Kei Hattori, Koichi Matsuno, Seiji Morita
  • Patent number: 9894271
    Abstract: A pattern inspection apparatus according to an embodiment includes an image capture and an output part. The image capture captures an image of a second pattern of an inspection target object obtained by enlarging the inspection target object having a first pattern. The output part outputs position information of the first or second pattern corresponding to divergent portions between a reference data generated from design data of the first pattern and a captured data generated by the image capture, other than prediction positions of first defects occurring when the inspection target object is enlarged.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Ryoji Yoshikawa, Tatsuhiko Higashiki, Seiji Morita, Takashi Hirano
  • Publication number: 20170271363
    Abstract: A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kamigaki, Isahiro Hasegawa, Shinichi Ito, Soichi Inoue, Tatsuhiko Higashiki, Kei Hattori, Koichi Matsuno, Seiji Morita
  • Publication number: 20160275365
    Abstract: A pattern inspection apparatus according to an embodiment includes an image capture and an output part. The image capture captures an image of a second pattern of an inspection target object obtained by enlarging the inspection target object having a first pattern. The output part outputs position information of the first or second pattern corresponding to divergent portions between a reference data generated from design data of the first pattern and a captured data generated by the image capture, other than prediction positions of first defects occurring when the inspection target object is enlarged.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 22, 2016
    Inventors: Ryoji Yoshikawa, Tatsuhiko Higashiki, Seiji Morita, Takashi Hirano
  • Publication number: 20140232032
    Abstract: In one embodiment, a lithography original checking method includes applying resin onto a first lithography original having a first concavo-convex pattern, hardening the resin, releasing the hardened resin from the first lithography original and producing a second lithography original having a second concavo-convex pattern corresponding to the first concavo-convex pattern, enlarging the second lithography original, detecting a defect on the enlarged second lithography original, and calculating a position of a defect on the first lithography original based on the position of the detected defect.
    Type: Application
    Filed: September 4, 2013
    Publication date: August 21, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryoji Yoshikawa, Daisuke Kawamura, Seiji Morita, Tatsuhiko Higashiki, Takashi Hirano
  • Patent number: 8609014
    Abstract: According to one embodiment, a template manufacturing method is a method for manufacturing a template for use in an imprint processing in which a pattern having irregularities are formed on a principal surface, and the pattern is brought into contact with a resist member formed on a substrate to be processed, to transfer the pattern to the resist member, the method including implanting charged particles at least into the bottoms of concave portions of the template.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Azuma, Tatsuhiko Higashiki, Kyoichi Suguro
  • Patent number: 8174669
    Abstract: There is disclosed is a liquid immersion optical tool, which comprises a light source, an optical lens system, a stage which moves an object base on which an object is to be placed, a head comprising a liquid immersion medium fluid supply device and a liquid immersion medium fluid discharge device to provide a layer of liquid immersion medium fluid between the optical lens system and the object, a fence which limits a region of the layer of liquid immersion medium fluid, and a cleaning device which cleans a portion having been contacted with the liquid immersion medium fluid by means of a cleaning solution.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiko Higashiki, Hiroshi Tomita
  • Patent number: 8122385
    Abstract: In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum dimensions of the mask pattern are smaller than a specific threshold value set near the exposure wavelength, the region is calculated using a high-accuracy model and the other regions are calculated using a high-speed model.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Tatsuhiko Higashiki, Toshiya Kotani, Satoshi Tanaka, Takashi Sato, Akiko Mimotogi, Masaki Satake
  • Publication number: 20120009799
    Abstract: According to one embodiment, a template manufacturing method is a method for manufacturing a template for use in an imprint processing in which a pattern having irregularities are formed on a principal surface, and the pattern is brought into contact with a resist member formed on a substrate to be processed, to transfer the pattern to the resist member, the method including implanting charged particles at least into the bottoms of concave portions of the template.
    Type: Application
    Filed: June 1, 2011
    Publication date: January 12, 2012
    Inventors: Tsukasa AZUMA, Tatsuhiko Higashiki, Kyoichi Suguro
  • Publication number: 20110229826
    Abstract: This invention discloses a method to form a resist pattern on a to-be-processed substrate by immersion exposure. A resist film is formed on the central portion of the upper surface of the to-be-processed substrate, on a bevel portion of the upper surface, which is obtained by chamfering the peripheral portion of the to-be-processed substrate, and on the end portion of the to-be-processed substrate. Pattern exposure for forming the latent image of a desired pattern on the resist film is executed while a liquid whose refractive index is higher than that of air exists between the resist film and a constituent element of a projection optical system of an exposure apparatus, which is nearest to the to-be-processed substrate. The resist film formed on the end portion of the to-be-processed substrate is removed by supplying a rinse solution to the end portion of the to-be-processed substrate after executing pattern exposure.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Inventors: Daisuke KAWAMURA, Eishi Shiobara, Tomoyuki Takeishi, Kei Hayasaki, Yasunobu Onishi, Shinichi Ito, Tatsuhiko Higashiki
  • Patent number: 7985958
    Abstract: According to an aspect of the invention, there is provided an electron beam drawing apparatus comprising at least one stage of a deflection amplifier and a deflection unit, a first storage section which stores shot information at a drawing time, a second storage section which stores a correction table indicating a relation between the shot information and an output voltage of the deflection amplifier, and an adjusting section which adjusts an output of the deflection amplifier based on the correction table stored in the second storage section and the shot information stored in the first storage section.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Nakasugi, Kazuo Tawarayama, Hiroyuki Mizuno, Takumi Ota, Noriaki Sasaki, Tatsuhiko Higashiki, Takeshi Koshiba, Shunko Magoshi
  • Patent number: 7968272
    Abstract: This invention discloses a method to form a resist pattern on a to-be-processed substrate by immersion exposure. A resist film is formed on the central portion of the upper surface of the to-be-processed substrate, on a bevel portion of the upper surface, which is obtained by chamfering the peripheral portion of the to-be-processed substrate, and on the end portion of the to-be-processed substrate. Pattern exposure for forming the latent image of a desired pattern on the resist film is executed while a liquid whose refractive index is higher than that of air exists between the resist film and a constituent element of a projection optical system of an exposure apparatus, which is nearest to the to-be-processed substrate. The resist film formed on the end portion of the to-be-processed substrate is removed by supplying a rinse solution to the end portion of the to-be-processed substrate after executing pattern exposure.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Kawamura, Eishi Shiobara, Tomoyuki Takeishi, Kei Hayasaki, Yasunobu Onishi, Shinichi Ito, Tatsuhiko Higashiki
  • Patent number: 7952071
    Abstract: Provided is a defect inspection apparatus and an inspection (or evaluation) method with highly improved accuracy, which would not be provided by the prior art, in the defect inspection apparatus used in a manufacturing process of a semiconductor device. Provided is a method for inspecting a sample surface with a projection type electron beam inspection apparatus, comprising the steps of: forming such an irradiation area on the sample surface by an electron beam generated from an electron gun 21 that has approximately a circular or elliptical shape of a size larger than a pattern on the sample surface; irradiating the electron beam substantially onto a center of the pattern on the sample surface; and forming an image on an electron detection plane of a detector from secondary electrons emanating from the sample surface in response to the irradiation of the electron beam for inspecting the sample surface.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: May 31, 2011
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Nobuharu Noji, Yoshihiko Naito, Hirosi Sobukawa, Masahiro Hatakeyama, Kenji Terao, Takeshi Murakami, Katsuya Okumura, Tatsuhiko Higashiki
  • Publication number: 20090305165
    Abstract: A wafer exposing method comprising EUV-exposing a product area, which is formed as a product chip, on a wafer and EB-exposing a peripheral area on the wafer, wherein the EB exposure of a wafer different from the wafer being EUV-exposed is performed while the EUV exposure of the wafer is performed.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 10, 2009
    Inventors: Ryoichi INANAMI, Tatsuhiko HIGASHIKI
  • Patent number: 7630052
    Abstract: An exposure processing system comprises an exposure apparatus to expose a resist on a wafer, a heating apparatus comprising heating apparatus units, the heating apparatus heating the exposed resist by a heating apparatus unit in the heating apparatus units, a developing apparatus comprising developing apparatus units, the developing apparatus developing the exposed and heated resist by a developing apparatus unit in the developing apparatus units, and a control apparatus to control the exposure apparatus by using correction data so that a wafer on process object being exposed, the correction data being data for correcting a dimensional dispersion of a resist pattern caused by a pair of heating apparatus unit and developing apparatus unit used for the wafer on the process object, the pair of heating and developing apparatus unit comprising a heating and developing apparatus unit in the heating and developing apparatus used for the wafer on the process object.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: December 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Kono, Nobuhiro Komine, Tatsuhiko Higashiki, Shoichi Harakawa, Makato Ikeda
  • Publication number: 20090284718
    Abstract: There is disclosed is a liquid immersion optical tool, which comprises a light source, an optical lens system, a stage which moves an object base on which an object is to be placed, a head comprising a liquid immersion medium fluid supply device and a liquid immersion medium fluid discharge device to provide a layer of liquid immersion medium fluid between the optical lens system and the object, a fence which limits a region of the layer of liquid immersion medium fluid, and a cleaning device which cleans a portion having been contacted with the liquid immersion medium fluid by means of a cleaning solution.
    Type: Application
    Filed: July 27, 2009
    Publication date: November 19, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiko Higashiki, Hiroshi Tomita
  • Publication number: 20090148782
    Abstract: An exposure method includes setting a photo mask into an exposure apparatus. The exposure apparatus includes an opening/closing unit configured to block a part of exposure light from a light source to the wafer. The photo mask having a product area in which a pattern to be used when a central part of a wafer is exposed is formed and peripheral exposure areas in each of which a pattern to be used when a peripheral area is exposed is formed. The peripheral exposure areas are formed to have a plurality of types of pattern densities. Then, a peripheral part of the wafer exposed. When exposing, the opening/closing unit is opened such that one or more of exposed photo mask areas selected from among the peripheral exposure areas has a pattern density corresponding to a shot position of the peripheral part.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 11, 2009
    Inventors: Takuya Kono, Tetsuro Nakasugi, Masamitsu Ito, Tatsuhiko Higashiki
  • Patent number: 7546178
    Abstract: An aligner evaluation system includes (a) an error calculation module configured to calculate error information on mutual optical system errors among a plurality of aligners; (b) a simulation module configured to simulate device patterns to be delineated by each of the aligners based on the error information; and (c) a evaluation module configured to evaluate whether each of the aligners has appropriate performances for implementing an organization of a product development machine group based on the simulated device pattern.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: June 9, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Kouno, Shigeki Nojima, Tatsuhiko Higashiki
  • Publication number: 20090141378
    Abstract: An optical element includes a substrate, a magnetostrictive film arranged on the substrate, a film thickness of the magnetostrictive film varying in accordance with intensity of a magnetic field, and a reflection film arranged on the magnetostrictive film and reflects light. An optical apparatus includes a stage including a holder provided with plural holes arranged in a carrying surface thereof for carrying an optical element provided with a magnetostrictive film arranged on a substrate, a film thickness of the magnetostrictive film varying in accordance with intensity of a magnetic field, and a reflection film arranged on the magnetostrictive film and reflecting light, plural magnetic field generation parts embedded in the plural holes, and a control mechanism for controlling the magnetic field generated by each of the plural magnetic field generation parts, and controlling the film thickness of the magnetostrictive film.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 4, 2009
    Inventors: Kazuo TAWARAYAMA, Tatsuhiko Higashiki, Iwao Higashikawa
  • Publication number: 20090026368
    Abstract: Provided is a defect inspection apparatus and an inspection (or evaluation) method with highly improved accuracy, which would not be provided by the prior art, in the defect inspection apparatus used in a manufacturing process of a semiconductor device. Provided is a method for inspecting a sample surface with a projection type electron beam inspection apparatus, comprising the steps of: forming such an irradiation area on the sample surface by an electron beam generated from an electron gun 21 that has approximately a circular or elliptical shape of a size larger than a pattern on the sample surface; irradiating the electron beam substantially onto a center of the pattern on the sample surface; and forming an image on an electron detection plane of a detector from secondary electrons emanating from the sample surface in response to the irradiation of the electron beam for inspecting the sample surface.
    Type: Application
    Filed: January 24, 2007
    Publication date: January 29, 2009
    Applicants: EBARA CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuharu Noji, Yoshihiko Naito, Hirosi Sobukawa, Masahiro Hatakeyama, Kenji Terao, Takeshi Murakami, Katsuya Okumura, Tatsuhiko Higashiki