Patents by Inventor Tatsuhiko Shirakawa

Tatsuhiko Shirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10546769
    Abstract: According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 eV from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuhiko Shirakawa, Kenji Takahashi, Eiji Takano, Masaya Shima
  • Publication number: 20160276200
    Abstract: According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 eV from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 22, 2016
    Inventors: Tatsuhiko SHIRAKAWA, Kenji TAKAHASHI, Eiji TAKANO, Masaya SHIMA
  • Patent number: 8338918
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Publication number: 20110241180
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 7993974
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 7849897
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20090194865
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Application
    Filed: September 24, 2008
    Publication date: August 6, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Publication number: 20080110546
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Application
    Filed: August 24, 2007
    Publication date: May 15, 2008
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20070235882
    Abstract: A semiconductor device includes a semiconductor substrate with an electrode pad on a main surface of the semiconductor substrate; a first penetrating electrode which includes a through hole formed through the semiconductor substrate in the thickness direction so as to reach a metallic bump formed on the electrode pad, an insulating resin formed to fill the through hole in and a conductor formed in the through hole with insulated from the semiconductor substrate by the insulating resin and electrically to connect the electrode pad and the rear surface of the semiconductor wafer; a semiconductor chip mounted on the rear surface of the semiconductor wafer so that a rear surface of the semiconductor chip is faced to the rear surface of the semiconductor wafer; and a wiring to electrically connect the first penetrating electrode and an electrode formed on the semiconductor chip.
    Type: Application
    Filed: April 9, 2007
    Publication date: October 11, 2007
    Inventors: Masahiro Sekiguchi, Kenji Takahashi, Hideo Numata, Tatsuhiko Shirakawa, Ninao Sato
  • Patent number: 6969913
    Abstract: There is here disclosed a semiconductor device comprising a first base material which is provided at least one semiconductor device mounted on one main surface, a plurality of first connection portions provided on the main surface and being electrically connected to the semiconductor device, and a plurality of second connection portions provided outside a region on which the semiconductor device is mounted on the main surface, and a second base material which is disposed facing other main surface of the first base material on a side opposite to the side on which the semiconductor device is mounted, bonded to an edge of the first base material, and provided a plurality of third connection portions provided outside a region on which the first base material is mounted on and being electrically connected to at least one of the second connection portions.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: November 29, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiko Shirakawa, Yoshiaki Sugizaki
  • Publication number: 20050151267
    Abstract: There is here disclosed a semiconductor device comprising a first base material which is provided at least one semiconductor device mounted on one main surface, a plurality of first connection portions provided on the main surface and being electrically connected to the semiconductor device, and a plurality of second connection portions provided outside a region on which the semiconductor device is mounted on the main surface, and a second base material which is disposed facing other main surface of the first base material on a side opposite to the side on which the semiconductor device is mounted, bonded to an edge of the first base material, and provided a plurality of third connection portions provided outside a region on which the first base material is mounted on and being electrically connected to at least one of the second connection portions.
    Type: Application
    Filed: March 10, 2004
    Publication date: July 14, 2005
    Inventors: Tatsuhiko Shirakawa, Yoshiaki Sugizaki