Patents by Inventor Tatsuhiko Tamura

Tatsuhiko Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6356326
    Abstract: An active matrix substrate for liquid crystal display in which an active element and address wiring are disposed in a matrix on an insulating substrate. The active element and address wiring are covered with a transparent insulating layer, and then a transparent electrode for display is disposed on the transparent insulating layer. The transparent electrode for display is connected to the active element through a contact hole created on the transparent insulating layer. In this structure, a difference in refractive index between an element insulating layer which is a part of the active element under the transparent display electrode and the transparent insulating layer, and a difference in refractive index between the element insulating layer and insulating substrate are both set to within 0.2. This allows to obtain a liquid crystal display with satisfactory display quality.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: March 12, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tatsuhiko Tamura, Takashi Hirose, Nobuyuki Tsuboi
  • Patent number: 5303072
    Abstract: An improved arrangement of a liquid crystal display device is provided in which the redundancy of a known but unwanted TFT (thin film transistor) defect is suppressed so that the yield per finished liquid crystal display device product can be increased without deterioration in the picture quality. Each pixel of the liquid crystal display device arranged at an intersection of one of scanning lines and one of signal lines is provided with two or three TFTs and also, a storage capacitor which is formed of a portion of a gate insulating layer and is sandwiched between its electrode and a preceding scanning line in the previous row using no extra masking procedure. The source, drain and gate electrodes of both the first and third TFTs are respectively coupled to the same signal line, the electrode of the same pixel and the adjacent scanning lines.
    Type: Grant
    Filed: June 26, 1991
    Date of Patent: April 12, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mamoru Takeda, Sadayoshi Hotta, Ichiro Yamashita, Tatsuhiko Tamura, Yoneharu Takubo
  • Patent number: 5185601
    Abstract: A liquid crystal display apparatus includes a transistor array substrate having formed thereon an array of pixel electrodes arranged in a matrix to form pixels, an array of switching thin film transistors arranged in a matrix for driving the pixels, respectively, gate bus lines arranged in rows for applying scanning signals to the switching thin film transistors, and source bus lines arranged in columns for applying display data signals to the switching thin film transistors. A counter substrate has formed thereon a common counter electrode confronting the pixel electrodes, and a liquid crystal layer is sandwiched between the transistor array substrate and the counter substrate. The transistor array substrate further has formed thereon a common electrode disposed below the pixel electrodes through an insulating layer for constituting auxiliary capacitors with the pixel electrodes.
    Type: Grant
    Filed: January 8, 1991
    Date of Patent: February 9, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mamoru Takeda, Tatsuhiko Tamura, Sadayoshi Hotta
  • Patent number: 4940934
    Abstract: In a method of electrically testing an active matrix substrate having a plurality of semiconductor switching devices, a row group of a plurality of parallel conductors and a column group of a plurality of parallel conductors, a gate electrode of each of the semiconductor switching devices being connected to one of the conductors of the row group, and a source electrode of each of the semiconductor switching devices being connected to one of the conductors of the column group, there are provided the steps of short-circuiting the conductors of the row group at both ends thereof; short-circuiting the conductors of the column group at both ends thereof; applying a predetermined voltage between the row and column groups of the conductors; and measuring a current flowing from the row group to the column group of the conductors. Moreover, in determining whether the active matrix substrate is defective, there is also provided the step of determining whether the following formula is satisfied or not:I.sub.1 .ltoreq.n.
    Type: Grant
    Filed: October 14, 1988
    Date of Patent: July 10, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takao Kawaguchi, Tatsuhiko Tamura, Etsuya Takeda