Patents by Inventor Tatsuhiro Kato

Tatsuhiro Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11926917
    Abstract: There is provided a composite plating material and a related technique thereof, the composite plating material including: a base material, and a composite plating layer on the base material, the composite plating layer comprising a composite material containing carbon particles and Sb in an Ag layer, with a carbon content of 6.0 mass % or more and a Sb content of 0.5 mass % or more.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 12, 2024
    Assignee: DOWA METALTECH CO., LTD.
    Inventors: Yukiya Kato, Hirotaka Kotani, Tatsuhiro Doi, Takao Tomiya, Hiroto Narieda
  • Patent number: 11920255
    Abstract: There are provided a composite plated product wherein a composite plating film of a composite material containing carbon particles in a silver layer is formed on a base material and wherein the amount of the carbon particles dropped out of the composite plating film is small, and a method for producing the same. After a composite plating film of a composite material containing carbon particles in a silver layer is formed on a base material (of preferably copper or a copper alloy) by electroplating using a silver-plating solution to which the carbon particles are added, a treatment for removing part of the carbon particles on the surface thereof is carried out.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: March 5, 2024
    Assignee: Dowa Metaltech Co., Ltd.
    Inventors: Hirotaka Kotani, Yukiya Kato, Tatsuhiro Doi, Takao Tomiya, Hiroto Narieda
  • Publication number: 20170158527
    Abstract: A water purifier-use cartridge includes a container main body having a filtering medium container and a lid portion bonded to the opening end side of the filtering medium container and a filtering medium in the filtering medium container. The lid portion has a water intake port and a water discharge port, a first water passage communicating with the water intake port is formed on an outer side of the filtering medium in the filtering medium container. The filtering medium is molded activated carbon having a second water passage and a hollow fiber membrane is configured to be in touch with the second water passage. The molded activated carbon and the hollow fiber membrane are disposed along a central axis direction of the filtering medium container, the water purifier-use cartridge is configured such that water flows from the first water passage to the second water passage through the molded activated carbon.
    Type: Application
    Filed: June 24, 2015
    Publication date: June 8, 2017
    Applicant: Mitsubishi Rayon Co., Ltd.
    Inventors: Yoshinobu KAWAI, Satoshi SUZUKI, Yukio KOBAYASHI, Shouzou KIMURA, Tatsuhiro KATO, Kenji HONJOU
  • Publication number: 20150197427
    Abstract: A pot type water purifier capable of obtaining a mixed liquid including purified water and an additive uniformly mixed in the purified water without the need of stirring in a container such as a cup after pouring out. The pot type water purifier of the present invention includes a body container with internal space and an upper opening; a raw water reservoir provided to an upper part of the internal space; a water purification cartridge communicating with the raw water reservoir; a purified water reservoir formed below the water purification cartridge, the purified water reservoir housing purified water resulting from filtration through the water purification cartridge; a pouring lip for purified water in the purified water reservoir; and stirring means provided to the body container to stir the purified water.
    Type: Application
    Filed: July 19, 2013
    Publication date: July 16, 2015
    Applicant: Mitsubishi Rayon Co., Ltd.
    Inventors: Kyoko Hattori, Tatsuhiro Kato, Hatsumi Takeda
  • Patent number: 7580317
    Abstract: A semiconductor memory circuit includes first and second bit lines making a first pair, third and fourth bit lines making a second pair, a memory cell having a first inverter coupled between the first pair, a second inverter coupled between the second pair, a third inverter coupled between first and third bit lines and a fourth inverter coupled between second and fourth bit lines. The memory cell further includes a first access switch inserted between first bit line and the first inverter, second access switch inserted between second bit line and the second inverter, third access switch inserted between third bit line and the third inverter and fourth access switch inserted between fourth bit line and the fourth inverter.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuhiro Kato
  • Publication number: 20080159051
    Abstract: A semiconductor memory circuit includes first and second bit lines making a first pair, third and fourth bit lines making a second pair, a memory cell having a first inverter coupled between the first pair, a second inverter coupled between the second pair, a third inverter coupled between first and third bit lines and a fourth inverter coupled between second and fourth bit lines. The memory cell further includes a first access switch inserted between first bit line and the first inverter, second access switch inserted between second bit line and the second inverter, third access switch inserted between third bit line and the third inverter and fourth access switch inserted between fourth bit line and the fourth inverter.
    Type: Application
    Filed: December 19, 2007
    Publication date: July 3, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Tatsuhiro Kato
  • Patent number: 7196945
    Abstract: A semiconductor memory has a plurality of memory cells having a single-ended digit structure. When reading data from a selected memory cell, a digit voltage outputted from the selected memory cell is compared with a reference voltage. If the digit voltage is higher, it is outputted as High level; if the digit voltage is lower, it is outputted as Low level. The semiconductor memory further has a plurality of dummy cells with different current capacity to generate a plurality of different levels of reference voltages.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: March 27, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuhiro Kato
  • Publication number: 20050024940
    Abstract: A semiconductor memory has a plurality of memory cells having a single-ended digit structure. When reading data from a selected memory cell, a digit voltage outputted from the selected memory cell is compared with a reference voltage. If the digit voltage is higher, it is outputted as High level; if the digit voltage is lower, it is outputted as Low level. The semiconductor memory further has a plurality of dummy cells with different current capacity to generate a plurality of different levels of reference voltages.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 3, 2005
    Applicant: NEC Electronics Corporation
    Inventor: Tatsuhiro Kato
  • Patent number: 6300651
    Abstract: A semiconductor device capable of making an interstitial space between adjacent two of pads and thereby decreasing a chip size without arising the difference of accessing speeds between banks. The semiconductor device has a center bonding structure including plural memory arrays (101 in FIG. 1), first peripheral circuit element groups (102 in FIG. 1) including amplifying circuit element, driving circuit element and the like which require to be arranged in symmetry relative to center bonding pads, second peripheral circuit element groups (103 in FIG. 1) including input/output circuit element, logic circuit element and the like which do not require the symmetrical arrangement, and pads (104 in FIG. 1). The second peripheral circuit element groups are essentially positioned on one side relative to the sequence of the pads.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: October 9, 2001
    Assignee: NEC Corporation
    Inventor: Tatsuhiro Kato
  • Patent number: 4998176
    Abstract: A liner for a floppy disk which comprises a nonwoven fabric and a high molecular resin attached thereto, said nonwoven fabric containing thermoplastic fibers and being of a structure wherein a thermocompression-bonded part and a non compression-bonded part are present and the form of the fabric is maintained through the thermocompression-bonded part, and a process for producing a liner for a floppy disk which comprises partially thermocompression-bonding a sheet-formed fiber aggregate containing thermoplastic fibers and then attaching a high molecular resin thereto.
    Type: Grant
    Filed: March 8, 1989
    Date of Patent: March 5, 1991
    Assignee: Mitsubishi Rayon Co., Ltd.
    Inventors: Sigeru Takemae, Akira Aoki, Tatsuhiro Kato, Tadakatu Nozawa, Isamu Makihara, Masanori Ito