Abstract: According to one embodiment, an isolator includes first and second conductive members, and first second, and third insulating members. The first conductive member includes first, second, and third partial regions. The third partial region is between the first and second partial regions. The second conductive member is electrically connected to the first conductive member. The second conductive member includes fourth and fifth partial regions. The fourth partial region is between the third and fifth partial regions. The first insulating member includes first and second insulating regions. The fifth partial region is between the first and second insulating regions. The second insulating member includes third and fourth insulating regions. The fourth partial region is between the third and fourth insulating regions. The third insulating member includes first and second portions.

Abstract: A drying device according to an embodiment dries a surface of an article by blowing hot air, and includes a drying chamber including a hot air supply port that blows the hot air, an infrared camera acquiring temperature distribution information that is information related to a temperature distribution inside the drying chamber, and a controller controlling a drying condition inside the drying chamber. The controller acquires corrected temperature distribution information by performing lock-in analysis of the temperature distribution information to remove noise from the temperature distribution information, and controls the drying condition based on the corrected temperature distribution information and based on a temperature distribution model that is a model related to the temperature distribution inside the drying chamber and is pre-generated using machine learning.

Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third semiconductor regions, first and second insulating parts, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor regions are provided selectively on the second semiconductor region. The first insulating part is arranged with the third and second semiconductor regions, and a portion of the first semiconductor region. The second electrode is provided inside the first insulating part. The gate electrode is provided inside the first insulating part and electrically isolated from the second electrode. The third electrode is provided on the second and third semiconductor regions. The third electrode includes a contact part provided between the third semiconductor regions. The second insulating part is provided between the first semiconductor region and the contact part.

Abstract: According to one embodiment, an isolator includes first and second conductive members, and first second, and third insulating members. The first conductive member includes first, second, and third partial regions. The third partial region is between the first and second partial regions. The second conductive member is electrically connected to the first conductive member. The second conductive member includes fourth and fifth partial regions. The fourth partial region is between the third and fifth partial regions. The first insulating member includes first and second insulating regions. The fifth partial region is between the first and second insulating regions. The second insulating member includes third and fourth insulating regions. The fourth partial region is between the third and fourth insulating regions. The third insulating member includes first and second portions.

Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.

Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.

Abstract: According to one embodiment, a processing system includes a chamber, a supplier, a detector, and a controller. The chamber is configured to store a processing object inside. The supplier is configured to supply a plurality of particles and a gas inside the chamber. The detector is configured to detect a state of air flow in a vicinity of the processing object. The controller is configured to control the supplier based on a detection value from the detector. The controller determines generation of a vortex based on data regarding a steady state of the air flow and the detection value from the detector, and controls the supplier to stop supply of the plurality of particles when the generation of the vortex is determined.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third semiconductor regions, first and second insulating parts, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor regions are provided selectively on the second semiconductor region. The first insulating part is arranged with the third and second semiconductor regions, and a portion of the first semiconductor region. The second electrode is provided inside the first insulating part. The gate electrode is provided inside the first insulating part and electrically isolated from the second electrode. The third electrode is provided on the second and third semiconductor regions. The third electrode includes a contact part provided between the third semiconductor regions. The second insulating part is provided between the first semiconductor region and the contact part.

Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a stacked body, and a second insulating film. A first insulating film and an electrode film are alternately stacked in the stacked body so as to extend in a first direction along an upper surface of the substrate. The stacked body includes an end portion in the first direction, a shape of the end portion being a staircase shape. The second insulating film is provided in first and second regions, the end portion being provided in the first region, the second region being contiguous to the first region in the first direction. The second insulating film includes a part in which a width of a second direction in the second region is smaller than a width of the second direction in the first region, the second direction crossing the first direction and along the upper surface of the substrate.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a circuit portion, a stacked body, at least one columnar member, a device isolation portion, and at least one first support member. The columnar member is in contact with an interconnect layer, and includes a contact extending in a stacking direction of a plurality of electrode films in the stacked body. The device isolation portion is provided in the stacked body and extends in a first direction and the stacking direction. The first support member is provided in the stacked body, extends in the stacking direction, and is located on the device isolation portion in a second direction crossing the first direction and along the upper surface of the substrate.

Abstract: According to an embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film, a first structure body, and a first connection portion. The stacked body includes a first conductive layer and a second conductive layer. The semiconductor pillar extends in the first direction through the stacked body. The memory film provides between the stacked body and the semiconductor pillar. The first conductive layer includes a first region and a second region. The first region does not overlap the second conductive layer in the first direction. The second region overlaps the second conductive layer in the first direction. The first structure body extends in the first direction through the first region to a position of a front surface of the first region. The first connection portion is electrically connected to the first conductive layer.

Abstract: A nonvolatile semiconductor storage device includes a NAND string including memory cells disposed in a first direction and a select gate disposed first-directionally adjacent to a first memory cell located at an end of the memory cells. A first gap is disposed between the memory cells and a second gap is disposed between the first memory cell and the select gate. Further, in a cross sectional shape, an upper end of the second gap is higher than an upper end of a first gap and an upper portion of the second gap is curved.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells.