Patents by Inventor Tatsuhiro Souda

Tatsuhiro Souda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10333803
    Abstract: A relay apparatus includes a memory and a processor coupled with the memory. The processor is configured to determine whether a frame received from a first device is to be discarded. The frame includes first information set at a first communication layer and second information set at a second communication layer different from the first communication layer. The processor is configured to transmit the frame to a second device upon determining that the frame is not to be discarded. The second device is set as a destination in the first information. The processor is configured to extract third information from the second information upon determining that the frame is to be discarded. The processor is configured to output the third information.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: June 25, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiro Miura, Satoru Fukuda, Masafumi Inaoka, Tatsuhiro Souda
  • Patent number: 10291491
    Abstract: A relay apparatus includes a memory and a processor coupled with the memory. The processor is configured to determine whether a frame received from a first device is to be discarded. The frame includes first information set at a first communication layer and second information set at a second communication layer different from the first communication layer. The processor is configured to transmit the frame to a second device upon determining that the frame is not to be discarded. The second device is set as a destination in the first information. The processor is configured to extract third information from the second information upon determining that the frame is to be discarded. The processor is configured to output the third information.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: May 14, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiro Miura, Satoru Fukuda, Masafumi Inaoka, Tatsuhiro Souda
  • Patent number: 9760421
    Abstract: An information processing device includes a plurality of processors. One of the plurality of processors is configured to: acquire a first code from a plurality of codes included in a program to be emulated; determine whether or not that a plurality of native codes corresponding to the acquired first code are for the atomic operation and that the first code accesses a memory; and generate a modified native code string with delay in which a certain code for delaying the completion of executing the plurality of native codes is inserted in the plurality of native codes corresponding to the first code when the one of the plurality of processors determined that the plurality of native codes corresponding to the first code are not for the atomic operation and that the first codes accesses the memory.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Tatsuhiro Souda, Satoru Fukuda, Tomohiro Miura, Masafumi Inaoka
  • Publication number: 20170104642
    Abstract: A relay apparatus includes a memory and a processor coupled with the memory. The processor is configured to determine whether a frame received from a first device is to be discarded. The frame includes first information set at a first communication layer and second information set at a second communication layer different from the first communication layer. The processor is configured to transmit the frame to a second device upon determining that the frame is not to be discarded. The second device is set as a destination in the first information. The processor is configured to extract third information from the second information upon determining that the frame is to be discarded. The processor is configured to output the third information.
    Type: Application
    Filed: September 21, 2016
    Publication date: April 13, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Tomohiro MIURA, Satoru Fukuda, Masafumi lnaoka, Tatsuhiro Souda
  • Publication number: 20160275001
    Abstract: An information processing device includes a plurality of processors. One of the plurality of processors is configured to: acquire a first code from a plurality of codes included in a program to be emulated; determine whether or not that a plurality of native codes corresponding to the acquired first code are for the atomic operation and that the first code accesses a memory; and generate a modified native code string with delay in which a certain code for delaying the completion of executing the plurality of native codes is inserted in the plurality of native codes corresponding to the first code when the one of the plurality of processors determined that the plurality of native codes corresponding to the first code are not for the atomic operation and that the first codes accesses the memory.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 22, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuhiro Souda, Satoru Fukuda, Tomohiro Miura, Masafumi lnaoka