Abstract: An encoding apparatus includes: an orthogonal transformation unit configured to orthogonally transform image data of a predetermined block size; a binarization unit configured to binarize the image data outputted from the orthogonal transformation unit; an arithmetic encoding unit configured to arithmetically encode the binary data generated by the binarization unit; and a prediction unit configured to predict, from the binary data, whether or not the amount of arithmetically encoded data generated by the arithmetic encoding unit exceeds a permissible maximum code amount based on a predetermined encoding standard. The encoding apparatus performs, when the prediction result is that the amount of arithmetically encoded data exceeds the maximum code amount, control to prevent the arithmetic encoding by the arithmetic encoding unit from being performed to the binary data corresponding to the prediction result.

Abstract: An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

Abstract: According to the present invention, there is provided an image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to recei

Abstract: The invention includes: a bitstream updating output unit configured to receive a bitstream and update a syntax element located at a beginning of the bitstream according to a code length thereof and outputs the syntax element; a bitstream decoding unit configured to decode, in response to a decode request, a variable-length code of the syntax element outputted from the bitstream updating output unit; a zerosLeft updating unit configured to update zerosLeft based on a specific syntax element decoded by the bitstream decoding unit; a run_before remaining number updating unit configured to update a run_before remaining number based on a specific syntax element decoded by the bitstream decoding unit; and a syntax selection unit configured to select a syntax element to be decoded by the bitstream decoding unit. Thus, multiple zero run_before syntaxes and one non-zero run_before syntax, or multiple zero run_before syntaxes are decoded all at once.

Abstract: When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.

Abstract: The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.

Abstract: An image processing apparatus includes: a frame memory; a buffer memory that stores pixel values of macroblocks of a first region including a first macroblock; a deblocking filter unit that is operable to: (1) read out the pixel values of the first region from the buffer memory; (2) apply the deblocking filter to the first macroblock; and (3) store the pixel values back into the buffer memory; and a pixel transfer unit that is operable to: (4) transfer pixel values of a macroblock not included in a second region that includes a second macroblock to be processed next to the first macroblock, from the buffer memory to the frame memory; and (5) transfer pixel values of a macroblock included in the second region but not included in the first region, from the frame memory to the buffer memory.

Abstract: A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

Abstract: A system for decoding a variable-length codeword includes a buffer circuit storing the codeword, a detection circuit detecting the number of bits of a prefix portion of the codeword by use of a detection table while updating the codeword, an extraction circuit extracting a codeword of a suffix portion of the codeword based on the number of bits of the prefix portion while updating the codeword, and a first decoding circuit decoding the codeword base on the number of bits of the prefix portion and the codeword of the suffix portion.

Abstract: A system for decoding a variable-length codeword includes a buffer circuit storing the codeword, a detection circuit detecting the number of bits of a prefix portion of the codeword by use of a detection table while updating the codeword, an extraction circuit extracting a codeword of a suffix portion of the codeword based on the number of bits of the prefix portion while updating the codeword, and a first decoding circuit decoding the codeword base on the number of bits of the prefix portion and the codeword of the suffix portion.

Abstract: The present invention provides a moving picture format variable length code (VLC) decoder that decodes at a high speed. The VLC decoder includes an input data memory, which is stored with a pixel data coefficient string in moving picture format, a table reference device, which is stored with table reference data and receives memory data from the input data memory, table storage memory including a reference table, which is stored with parametric data, receives table reference data ARG from the table reference device, and transmits parametric data to the table reference device, and output data memory, which receives reference table data made from a coefficient flag output from the table reference device and the last coefficient flag.

Abstract: A logic circuit comprising a flip-flop chain circuit which is utilized in a scan test of a combinational circuit, the flip-flop chain circuit including a plurality of flip-flops each of which is provided with a selector.

Abstract: A logic circuit comprising a flip-flop chain circuit which is utilized in a scan test of a combinational circuit, the flip-flop chain circuit including a plurality of flip-flops each of which is provided with a selector.